[54] LEAD CONNECTIONS MEANS FOR STACKED TAB PACKAGED IC CHIPS
[75] Inventors: Watanabe Masayuki, Yokohama;
Sugano Toshio, Kokubunji; Tsukui
Seiichiro, Komoro; Ono Takashi,
Akita; Wakashima Yoshiaki,
Kawasaki, all of Japan
[73] Assignees: Akita Electronics Co. Ltd.; Hitachi Ltd.; Hitachi Semiconductor Ltd., Japan
[21] Appl. No.: 796,873
[22] Filed: Nov. 25,1991
Related U.S. Application Data
[63] Continuation of Ser. No. 607,411, Oct. 31, 1990, abandoned, which is a continuation of Ser. No. 209,739, Jun. 22, 1988, Pat. No. 4,982,265.
[30] Foreign Application Priority Data
Jun. 24, 1987 [JP] 'Japan 62-155478
Sep. 11, 1987 [JP] Japan 62-226307
[51] Int. CI.5 H01L 23/16; H01L 23/48;
H01L 29/44; H01L 29/60
[52] U.S. CI 357/75; 357/70;
357/69; 357/80; 357/74; 174/52.4
[58] Field of Search 357/75, 70, 69, 80,
357/74; 174/52.4
[56] References Cited
U.S. PATENT DOCUMENTS
4,109,096 8/1978 Dehaine 357/70
4,363,076 12/1982 Mclver 357/69
4,763,188 8/1988 Johnson 357/75
FOREIGN PATENT DOCUMENTS
075981 6/1977 Japan 357/69
255046 11/1986 Japan .
090958 4/1987 Japan 357/75
OTHER PUBLICATIONS
Tsuda et al., "The LSI Package is Diversifying its Technological Performance ... ", Ed. Nikkei Electronics, p. 148.
Primary Examiner—Rolf Hille
Assistant Examiner—Robert Limanek
Attorney, Agent, or Firm—Pennie & Edmonds
[57] ABSTRACT
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
13 Claims, 23 Drawing Sheets
