Distribution network switch for very large gigabit switching architecture

United States Patent [w]

Yang et al.

US005856977A [ii] Patent Number: [45] Date of Patent:

5,856,977 Jan. 5, 1999

[54] DISTRIBUTION NETWORK SWITCH FOR VERY LARGE GIGABIT SWITCHING ARCHITECTURE

[76] Inventors: Muh-rong Yang, 2F-1, No. 6 Ln 13, Ching-hau Street, Ching-Mei, Taipei; Gin-Kou Ma, 9, In. 328, Sec. 3, Chung Hsing Rd., Chutung, both of Taiwan

[21] Appl. No.: 856,557

[22] Filed: May 15, 1997

[51] Int. C I. H04L 12/28

[52] U.S. CI 370/411; 370/395; 370/411;

370/412; 370/413

[58] Field of Search 370/411, 389,

370/395, 412, 428, 413, 419, 361, 370, 371, 372, 376, 378, 380, 387, 388; 340/825.79,

825.8

[56] References Cited

U.S. PATENT DOCUMENTS

5,157,654 10/1992 Cisneros 370/414

5,179,552 1/1993 Chao 370/427

5,412,646 5/1995 Cyr et al 370/411

5,724,352 3/1998 Cloonan et al 370/395

Primary Examiner—Douglas W. Olms

Assistant Examiner—Phirin Sam

Attorney, Agent, or Firm—Proskauer Rose LLP

[57] ABSTRACT

An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an NxN first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the NxN network are p* groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to [log2N/log2p]_1 and p equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/p. To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are p* groups of (N/p*)x(N/p*) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of p* groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.

28 Claims, 8 Drawing Sheets