Address translation buffer system and method for invalidating address ...

United States Patent [w]

Kawamoto et al.

[54] ADDRESS TRANSLATION BUFFER SYSTEM AND METHOD FOR INVALIDATING ADDRESS TRANSLATION BUFFER, THE ADDRESS TRANSLATION BUFFER PARTITIONED INTO ZONES ACCORDING TO A COMPUTER ATTRIBUTE

[75] Inventors: Kqji Kawamoto; Hiromichi Kainoh;

Kuniki Tohbaru, all of Hadano, Japan

[73] Assignees: Hitachi, Ltd., Tokyo; Hitachi

Information Technology Co., Ltd.,

Hadano, both of Japan

[21] Appl. No.: 08/714,395

[22] Filed: Sep. 16, 1996

[30] Foreign Application Priority Data

Sep. 19, 1995 [JP] Japan 7-239385

[51] Int. CI.6 G06F 12/10

[52] U.S. CI 711/207; 711/6

[58] Field of Search 711/206, 207,

711/6, 205

[56] References Cited

U.S. PATENT DOCUMENTS

4,456,954 6/1984 Bullions, III et al 711/207

4,779,188 10/1988 Gum et al 395/500

4.816,991 3/1989 Watanable et al 711/206

5,317,705 5/1994 Gannon et al 711/207

5,317,710 5/1994 Ara et al 711/207

FOREIGN PATENT DOCUMENTS

A-60-138654 7/1985 Japan .
A-4-81951 3/1992 Japan .

Illllllllllllllllllllllllllllllllllllllllllllli

US005924127A

[ii] Patent Number: 5,924,127

[45] Date of Patent: Jul. 13,1999

A-5-151085 6/1993 Japan .

OTHER PUBLICATIONS

Coscarella et al., "System for Purging TLB" IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 910-911.

Primary Examiner—Eddie P. Chan

Assistant Examiner—Yamir Encarnacion

Attorney, Agent, or Firm—Antonelli, Terry, Stout & Kraus,

LLP

[57] ABSTRACT

An address translation buffer system in which a searching time of an address translation buffer is shortened. The address translation buffer includes an address translation buffer connected to a translation table for translating a virtual address to a real address, the address translation buffer containing a plurality of columns holding a plurality of entries each having a pair of the virtual address and the real address translated based on the translation table and also having a virtual machine classification indicative of a type of the virtual address, a plurality of column control circuits for specifying columns of the address translation buffer with a combination of a lower part of the virtual address and the virtual machine classification as an entry, and circuits, in accordance with an invalidation instruction for purging one of the entries of the address translation buffer, for searching one of the columns of the address translation buffer having one of the entries of the address translation buffer coincided with the virtual machine classification entry of the invalidation instruction and for invalidating the entry including a specified field. It is unnecessary to search a group of columns having values other than the specified virtual machine classification.

21 Claims, 14 Drawing Sheets