[54] INPUT LOGIC SIGNAL BUFFER CIRCUITS
[75] Inventor: Chul-soo Kim, Suwon, Rep. of Korea
[73] Assignee: Samsung Electronics Co., Ltd., Suwon, Rep. of Korea
[21] Appl. No.: 639,922
[22] Filed: Apr. 24,1996
[30] Foreign Application Priority Data
Apr. 24, 1995 [KR] Rep. of Korea 95-9639
[51] Int CI.6 H»3K 19/0175
[52] U.S. CI 326/115; 326/17; 326/86;
326/121
[58] Field of Search 326/17, 31, 63,
326/83, 86, 115, 121; 327/52, 53, 54
[56] References Cited
U.S. PATENT DOCUMENTS
5,408,146 4/1995 Nguyen et al 326/115 X
5,440,248 8/1995 Brown et al 326/121 X
5,444,396 8/1995 Soneda 326/121 X
Primary Examiner—David R. Hudspeth
Attorney, Agent, or Firm—Myers, Bigel, Sibley & Sajovec,
L.L.P.
[57] ABSTRACT
An input logic signal buffer circuit includes a differential amplifier which is responsive to an input logic signal and to a reference signal, to produce an output logic signal at an output node thereof. The input logic signal buffer circuit also includes a bypass amplifier which is electrically connected between the output logic signal and the output node. The bypass amplifier supplies additional current to the output node in response to logic level transitions of the input logic signal. The bypass amplifier preferably is a field effect transistor, the gate of which is electrically connected to the input logic signal and the source and drain of which are serially connected between the output node and a current limiting resistor. Logic level transitions with reduced delays, particularly at low power supply voltages, are thereby provided.
18 Claims, 4 Drawing Sheets
