United States Patent [19] [H] Patent Number: 4,542,340
Chakravarti et al. [45] Date of Patent: Sep. 17, 1985
[54] TESTING METHOD AND STRUCTURE FOR LEAKAGE CURRENT CHARACTERIZATION IN THE MANUFACTURE OF DYNAMIC RAM CELLS
[75] Inventors: Satya N. Chakravarti, Hopewell
Junction, N.Y.; Paul L. Garbarino,
Ridgefield, Conn.; Donald A. Miller,
Fishkill, N.Y.
[73] Assignee: IBM Corporation, Hopewell
Junction, N.Y.
[21] Appl. No.: 454,900
[22] Filed: Dec. 30, 1982
[51] Int. CI* G01R 31/26; G01R 31/00
[52] U.S. CI 324/158 R; 29/574;
324/73 R; 324/158 D; 324/158 T
[58] Field of Search 324/158 R, 73 R, 60 C;
29/574; 371/21; 324/158 T, 158 D, 158 SC
[56] References Cited
U.S. PATENT DOCUMENTS
3,387,286 6/1968 Dennard 365/222
3,811,076 5/1974 Smith, Jr 357/41
A testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells; the testing structure includes two large gate-controlled diodes, each diode having a diffused junction which is substantially identical with that of the other diode, the gates of the diodes having different perimeter-to-area ratios, such that when testing is carried out, the leakage current components due to the contribution of the thin oxide area can be isolated from the perimeter-contributed components of the isolating thick oxide; dynamic testing can also be performed and, because of the small area for the test site, an "on chip" amplifier can be provided at the site.
14 Claims, 5 Drawing Figures
