Device for processing digital signals first coded by means of variable ...

United States Patent [i9]

Decotignie et al.

[ii]

[45]

lllllll! Ill

US005502571A Patent Number: 5,502,571

Date of Patent: Mar. 26,1996

[54] DEVICE FOR PROCESSING DIGITAL SIGNALS FIRST CODED BY MEANS OF VARIABLE LENGTH CODING AND DEVICE FOR INVERSELY PROCESSING SIGNALS THUS PROCESSED

[75] Inventors: Philippe Decotignie, Paris; Sabine Jourdan, Savigny-Sur-Orge, both of France

[73] Assignee: U.S. Philips Corporation, New York, N.Y.

[21] Appl. No.: 148,109

[22] Filed: Nov. 4, 1993

[30] Foreign Application Priority Data

Nov. 18, 1992 [FR] France 92 13855

Jun. 9, 1993 [FR] France 93 06923

[51] Int. CI.6 H04N 5/76; H04N 7/12

[52] U.S. CI 358/335; 348/388

[58] Field of Search 358/335, 342,

358/310; 348/384, 397, 408, 399, 388;

360/33.1

[56] References Cited

U.S. PATENT DOCUMENTS 4,907,101 3/1990 Keesen et al. .

5,047,852 9/1991 Hanyu et al 348/408

5,111,292 5/1992 Kuriacose et al 358/133

5,144,425 9/1992 Joseph 358/133

5,231,384 7/1993 Kuriacose 348/388

FOREIGN PATENT DOCUMENTS

0482888 4/1992 European Pat. Off. H04N 5/92

0501699 9/1992 European Pat. Off. H04N 7/13

9102430 2/1991 WIPO .

Primary Examiner—Tommy P. Chin

Assistant Examiner—-Robert Chevalier

Attorney, Agent, or Firm—Laurie E. Gathman; Leroy Eason

[57] ABSTRACT

Device for processing digital signals constituted by image blocks and hierarchically arranged types of data. This device comprises an addressable memory (40) for storing said signals, a circuit (10) for counting, per section, the number of bits corresponding in these signals to each type of data, a circuit (20) for assigning, to each of the image sections and in accordance with a given proportion, the number of bits to be transmitted in channels of different priorities, and at the output of said circuits a control circuit (30) for redistributing the bits for each of the sections and in packets of given lengths comprising at least the first bits of a block and possibly the leftover bits of the other blocks. The invention also relates to the device for inverse processing at the receiver end.

7 Claims, 2 Drawing Sheets

1

DEVICE FOR PROCESSING DIGITAL
SIGNALS FIRST CODED BY MEANS OF
VARIABLE LENGTH CODING AND DEVICE
FOR INVERSELY PROCESSING SIGNALS
THUS PROCESSED

BACKGROUND OF THE INVENTION

The invention relates to a device for processing, for transmission and/or storage, digital signals corresponding to a sequence of images and which have first been coded, at least in part, in accordance with a variable length coding method, said signals being constituted by image blocks of an intergral number M of types of data which can be arranged in accordance with a given hierarchy. The invention also relates to a device for inversely processing such signals before they are decoded, after the digital signals have already been processed as described and subsequently transmitted and/or stored. The invention may be used, for example 1 in the field of transmitting animated images and particularly television images.

A standard referred to as MPEG1 has recently been adopted by the "Moving Picture Expert Group" (MPEG) of the international standardization organization I.S.O for storing digital animated images. This standard defines a very efficient coding process for recording non-interlaced images in the OF format (Common Intermediate Format, 288 linesx352 pixels/line, 25 Hz, 1:1) but can also be used for any other image format. The coding methods which are compatible with said standard allow, for example compression of a digital television signal of 160 Mbits/s to 5 Mbits/s, i.e. in a ratio of 32/1, while preserving a very satisfactory image quality.

In current research it has been attempted to ascertain whether this standard may also be used for transmitting images and, for example and, television images. Unfortunately, the answer seems to be negative at the moment because of the Variable Length Coding (VLC) technique which is used for the MPEG1 standard and is associated with an orthogonal transform referred to as Discrete Cosine Transform (DCT) with which the spatial redundance of the image can be reduced. When a transmission error influences a bit of the digital data stream obtained after VLC coding, the decoder receives a code word whose length appears to be different from that of the transmitted code word, which the decoder does not recognize and so it no longer has a temporal reference for locating the start of the next code word. The result is that the subsequent code word is decoded in an erroneous manner and also the following code words are decoded erroneously; i.e., the error propagates. All the data decoded after the location of the first error are false until a new reference point constituted by a synchronization word has not appeared. As the latter are very numerous (for example, one in every 16 lines of the image), even a very weak error rate contributes to unacceptable image faults, due to propagation of these errors. There are techniques for reducing the error rate to very low values, making use of very powerful error correction codes, but these techniques increase the redundancy of the signals, which runs counter to the objective pursued by MPEG1.

Another technique with which, instead of correcting the error(s), the propagation of errors can be limited, is described in U.S. Pat. No. 4,907,101. The solution proposed in this document is that, based on the tact that each coded block contains a variable number of code words of different lengths, a packet (or unit) of a given capacity which is equal

2

to the average length B of the blocks between two successive synchronization words (i.e. in an image section) is defined and that at least the first bits of a block in this packet are transmitted. If a block is shorter than this packet, the leftover

5 bit locations will remain in this packet. If, in contrast, a block is longer than the packet, the leftover bits are placed in the locations which have been left available by the short blocks. Thus, all the packets of the transmitted bits have an equal length (with the possible exception of the last packet,

10 because the total number of bits of a section is not generally equal to a multiple of the number of blocks) and during decoding synchronization can be based on the marking of the starts of the packets of bits corresponding to each block. Thus, synchronization no longer poses any problem. Even if

15 one or several of these blocks are beset with transmission errors, these errors can no longer propagate to other blocks.

Unfortunately, this technique is not satisfactory because it cannot be applied to an assembly of different information components such as are present in an MPEG1 data stream.

20 In fact, it will hereinafter be evident that for the quality of the image certain ones of these information components are more important than the information components of the block itself, and their loss may impede the whole decoding process at the receiver end. Moreover, the majority of these

25 information components are coded in a differential manner, i.e. a prediction technique is used which is based on similar information components present in the previous blocks (by coding the difference between the previous information component and the current information component) and

30 every error in a block discontinues to propagate because of this relation to the previous information components.

SUMMARY OF THE INVENTION

35

A first object of the invention is to provide a device for processing digital signals which are of different lengths and thus have a variable importance justifying their arrangement in accordance with a given hierarchy, in which the propa

40 gation of errors is limited in spite of the existence of a prior variable length coding of these signals and without increasing the degree of redundance of information components contained in these signals. To this end the invention relates to a device as defined in

45 the opening paragraph and which is characterized in that it comprises:

(1) an addressable memory for storing the stream of bits of a digital signal which has been coded by variable length coding;

(2) a counting circuit also receiving said bit stream in order to determine and store the number of bits in said stream corresponding to each type of data in at least one image section, a section being defined as a whole

55 sub-assembly of data blocks which is preceded by a synchronizing signal;

(3) at the output of the counting circuit, a bit allocation circuit for assigning to each image section, and in accordance with a given proportion to be roughly taken

60 into account in an image or in a group of images, the number of bits to be transmitted and/or stored in each of a number N of channels of different priorities, these N numbers of bits being referred to as allocations;

(4) at the output of the channel bit allocation circuit, a 65 circuit for controlling the redistribution of bits of said

stream for each image section and in accordance with the following process: