[54] SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
[75] Inventor: William C. Plants, Santa Clara, Calif.
[73] Assignee: Actel Corporation, Sunnyvale, Calif.
[21] Appl. No.: 09/039,923 [22] Filed: Mar. 16, 1998
[51] Int. CI.7 H03K 19/177
[52] U.S. CI 710/126; 710/131; 326/37;
326/38; 326/39; 326/40; 365/185.01; 365/185.08;
365/185.11
[58] Field of Search 710/126, 128,
710/129, 131; 326/37, 38, 39, 40, 41; 365/185.01,
185.08, 185.11
[56] References Cited
U.S. PATENT DOCUMENTS
4,930,097 5/1990 Ledenbach et al 364/716
5,187,392 2/1993 Allen 307/465
5,198,705 3/1993 Galbraith et al 307/465
5,208,491 5/1993 Ebeling et al 307/465
5,222,066 6/1993 Grula et al 371/21.1
5.744.979 4/1998 Goetting 326/39
5.744.980 4/1998 McGowan et al 326/40
5,801,547 9/1998 Kean 326/40
5,809,281 9/1998 Steele et al 711/170
5.815.003 9/1998 Pedersen 326/39
5.815.004 9/1998 Trimberger et al 326/41
5,821,776 10/1998 McGowan 326/41
5.825.200 10/1998 Kolze 326/38
5.825.201 10/1998 Kolze 326/39
5.825.202 10/1998 Tavana et al 326/39
5,825,662 10/1998 Trimberger 364/491
5,828,230 10/1998 Young 326/41
5,828,538 10/1998 Apland et al 361/56
5,831,448 11/1998 Kean 326/41
5,835,998 11/1998 Pedersen 326/40
5,838,165 11/1998 Chatter 326/38
5,838,167 11/1998 Erickson et al 326/38
5,838,584 11/1998 Kazarian 364/491
5,838,892 11/1998 Wilson 714/799
5,838,954 11/1998 Trimberger 395/500
5,847,441 12/1998 Cutter et al 257/530
5,847,577 12/1998 Trimberger 326/38
5,848,005 12/1998 Cliff et al 365/230.03
5.850.151 12/1998 Cliff et al 326/39
5.850.152 12/1998 Cliff et al 326/40
5,850,564 12/1998 Ting et al 395/800.37
5.859.542 1/1999 Pedersen 326/39
5.859.543 1/1999 Kolze 326/41
5.859.544 1/1999 Norman 326/40
5,861,761 1/1999 Kean 326/41
5,869,981 2/1999 Agrawal et al 326/39
5,870,586 2/1999 Baxter 395/500
5,880,492 3/1999 Duong et al 257/209
5,880,512 3/1999 Gordon et al 257/530
5.880.597 3/1999 Lee 326/41
5.880.598 3/1999 Duong 326/41
5,883,526 3/1999 Reddy et al 326/41
5,883,850 3/1999 Lee et al 365/230.03
FOREIGN PATENT DOCUMENTS
0 415 542 A2 7/1990 European Pat. Off H03K 19/173
0 889 593 Al 5/1995 European Pat. Off H03K 19/173
Primary Examiner—Ayaz R. Sheikh
Assistant Examiner—Ario Etienne
Attorney, Agent, or Firm—-Jonathan H. Schafer
[57] ABSTRACT
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the passthrough interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks without being further connected to the SRAM bussing architecture.
3 Claims, 6 Drawing Sheets
