[54] HIGH BANDWIDTH PCI TO PACKET SWITCHED ROUTER BRIDGE HAVING MINIMIZED MEMORY LATENCY
[75] Inventor: Steven C. Miller, Livermore, Calif.
[73] Assignee: Silicon Graphics, Inc., Mountain View, Calif.
[21] Appl. No.: 08/780,781 [22] Filed: Jan. 9, 1997
[51] Int. CI. G06F 13/42
[52] U.S. CI 395/309; 395/308; 395/872;
395/585
[58] Field of Search 395/306, 308,
395/309, 311, 287, 292, 842, 848, 847, 856-857, 858-859, 881, 872, 584, 585, 586, 587; 711/118, 140, 141-146
[56] References Cited
U.S. PATENT DOCUMENTS
5,594,882 1/1997 Bell 711/212
5,664,117 9/1997 Shah et al 395/281
5,673,399 9/1997 Guthrie et al 395/308
5,761,450 6/1998 Shah 395/287
5,761,461 6/1998 Neal et al 395/309
5,771,359 6/1998 Galloway et al 395/308
Primary Examiner—Ayaz R. Sheikh
Assistant Examiner—Raymond N. Phan
Attorney, Agent, or Firm—-Wagner, Murabito & Hao
[57] ABSTRACT
In a computer system, a mechanism for minimizing memory latencies. An improved, high-speed packet switched router is used to route packets quickly and efficiently between the microprocessor and the main memory. The computer system also supports PCI devices by implementing a bridge which acts as an interface between the PCI bus and the packet switched router. In order to minimize the memory latencies for PCI based memory accesses through the bridge, a plurality of read and write buffers are implemented. Write gathering is used to gather a plurality of write transactions on the PCI bus into the write buffers and sent by the bridge as one cache line sized transfer to the routing mechanism. For PCI based read operations, data is pre-fetched from the main memory and stored in the read buffers. Thereby, PCI devices can access the read buffers multiple times to retrieve the requested data.
16 Claims, 4 Drawing Sheets
