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US007925808B2 <15) United States Patent <16) Patent No.: US 7,925,808 B2 Perego et al. (45) Date of Patent: Apr. 12, 2011 (54) MEMORY SYSTEM AND DEVICE WITH (56) References Cited SERIALIZED DATA TRANSFER U.S. PATENT DOCUMENTS (75) Inventors: Richard E Perego, San Jose, CA (US); 4,369,511 A * 1/1983 Kiniura et al. .............. .. 714/719 FrederickA Ware, Los Altos Hills, CA Q 59211113 , , g3.W3. ‘U81 21211222: 2/122% , , €OI1 (73) Assignee: Rambus Inc., Sunnyvale, CA (U S) 5,243,703 A 9/1993 Farmwald 5,315,560 A 5/1994 Nishimoto et al. ( * ) Notice: Subject to any disclaimer, the term of this Q giirfiiwald patent is extended or adjusted under 35 537293711 A * 3/1993 Okamoto ,,,,,,,,,,,,,,,,,,,, ,, 711/205 U.S.C. l54(b) by 524 days. 5,764,963 A 6/1993 Ware 5,765,020 A 6/1998 Barth (21) Anni, Noe 12,116,439 5,806,070 A 9/1998 Norman et 51. (Continued) (22) Ffledi May 71 2°08 FOREIGN PATENT DOCUMENTS (65) Prior Publication Data EP 0604309(€l i_ 6/(1394 on inue US 2008/0209141 A1 Aug. 28, 2008 OTHER PUBLICATIONS Related U.S. Application Data Response to Office Action dated Feb. 2, 2010, Chinese Patent Appli_ _ _ _ 65665 No. 200810098473.4 filed J55. 13, 2004. (63) Continuation of application No. 11/549,841, filed on Oct. 16, 2006, now Pat. No. 7,478,181, which is a (COHIi11L1ed) iZntiriLiat;%%eOf appliiicitiign I203‘ i1e0g3e%5908filed on Primary Examiner — Christopher B Shin an ’ ’nOW a ' 0' ’ ’ ' (74) Attorney, Agent, or Firm —Vierra Magen Marcus & (60) Provisional application No. 60/439,666, filed on Jan. DeNirO LLP 13, 2003 (57) ABSTRACT A memory system with serialized data transfer. The memory (51) Int. Cl. system includes within a memory controller and a plurality of G06F 13/38 (2006.01) memory devices. The memory controller receives a plurality G06F 13/00 (2006.01) of write data values from a host and outputs the write data (52) U.S. Cl. ........... .. 710/71; 710/74; 711/155, 365/221 values as respective Serial Streams Of biIS- Each Of the (58) Field of Classification Search .................. .. 710/74, mem°1'Y demes 16°61“ a‘1e*‘S‘°ne Ofthe Senal Streams °f

710/31-35, 52, 65-71; 365/120, 220-221; 711/154-155,156,170 See application file for complete search history.

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bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

15 Claims, 15 Drawing Sheets

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i ADDITIONAL RANK(S) OF MEiMORY DEVICES (OPTIONAL)
| I I‘ """""" " 4 A 3
I T ; ARRAY E l,21aA., l/218A, l/218A; 21a/11,?
I 1
ea I s E
I “Z1 = = MEM '- MEM = =
I
1 l | | | I . |
200 | l 1 : { 2211 { 221.: : 1
\n | I | | | 1 1
l :55? -1 -_1 __; .1
I_____5_____A'é1£“__5__IK£1B_'__V__ §B1.__
214 C wf wl’
_ _ _ _ _ __ ___!______Y._____ ____
I CONTROL PORT DQ D9 5°
I Q; DATA PORT 55
: 1 MEMORY INTERFACE 211 1

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MEMORY CONTROLLER Z11

CODED DATA BLOCK

/ HOST INTERFACE

TXTYT

R EQ MASK DATA

15*-T-'——T
(D

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U.S. PATENT DOCUMENTS

5,813,043 A * 9/1998 Iles et al. .................... .. 711/163 5,872,996 A 2/1999 Barth

5,896,545 A 4/1999 Barth

6,122,189 A 9/2000 Batra

6,151,239 A 11/2000 Batra

6,266,737 B1 7/2001 Ware

6,347,354 B1 2/2002 Abhyankar

6,401,167 B1 6/2002 Barth

6,578,126 B1 6/2003 MacLellan

6,757,789 B2 6/2004 Abhyankar

6,801,459 B2 10/2004 Riesenman et al.

6,826,663 B2 * 11/2004 Perego et al. ............... .. 711/156 6,952,367 B2 10/2005 Riesenman et al.

6,957,307 B2 10/2005 Riesenman et al.

7,143,329 B1 * 11/2006 Trimberger et al. ........ .. 714/746 7,165,177 B2 1/2007 Gilbert et al.

7,171,528 B2* 1/2007 Evans et al. ................. .. 711/156

7,216,187 B2 5/2007 Perego et al.

7,313,639 B2 12/2007 Perego 2003/0159039 A1 8/2003 Gilbert 2003/0179605 A1 9/2003 Riesenman 2003/0182519 A1 9/2003 Riesenman 2004/0093471 A1 5/2004 Riesenman 2007/0073926 A1 3/2007 Perego et al.

FOREIGN PATENT DOCUMENTS

EP 0883066 A3 12/1998

JP 03-122492 U 12/1991

JP 07-121351 A 5/1995

WO WO0215020 A2 2/2002 OTHER PUBLICATIONS

Office Action dated Feb. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933 filed Jan. 13, 2004.

English Translation of the Abstract of European Patent Publication No. EP0604309 dated Jun. 29, 1994.

Rambus Inc., “8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM—Preliminary Information,” Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.

“A Logical Overview of Direct Rambus Architecture,” Rambus, Inc., Mar. 1998, 150 pages.

Rambus Inc., “16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM—Advance Information,” Rambus Inc. Data Sheet, Jul. 1996, 61 pages.

“AMD-751 System Controller Data Sheeet”, AMD, Mar. 2000. “AMD-762 System Controller Data Sheet”, AMD, Dec. 2001. “FCRAM I IP CORE”, Lattice Semiconductor Corporation, Nov. 2004.

“Virtex Synthesizable High Performance SDRAM Controller”, XILINX, XAPP 134, Version 2.1, Sep. 10, 1999.

Notification of First Office Action, The Patent Office of the People’s Republic ofChina, Application No. 200480003983 .9 filed on Jan. 13, 2004, Jun. 4, 2007.

Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Jul. 11,2008.

Response to Final Office Action, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Aug. 26, 2008.

Notification of Second Office Action, The Patent Office of the People’s Republic of China, Application No. 200480003983.9 filed on Jan. 13, 2004, Aug. 15,2008.

Response to Japanese Office Action filedAug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933, filed Jan. 13, 2004.

English Translation of Response to Japanese Office Action filed Aug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006500933, filed Jan. 13,2004.

Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16,2006, Sep. 22, 2008.

Response to Chinese Office Action filed Jan. 5, 2011, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.

Chinese Office Action dated Nov. 8, 2010, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.

* cited by examiner

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MEMORYINTERFACE

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FIG 2

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TO STORAGE
SUBSYSTEM

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DATA VALUES BLOCK
F I 3 175 179
/ /
RECEIVE CODED DATA BLOCK AND WRITE D AT A STORE WRITE D AT A
MASKED-WRITE REQUEST, MASKED
VALUE MATCHES VALUE AT ADDRESS-
WRITE REQUEST INCLUDING ADDRESS, MASK KEY, SPECIFIED LOCATION
COMMAND AND MASK KEY

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