Non-blocking load buffer and a multiple-priority memory system for real-time ...

United States Patent [w]

Zuravleff et al.

US005812799A [ii] Patent Number: [45] Date of Patent:

5,812,799 Sep. 22, 1998

[54] NON-BLOCKING LOAD BUFFER AND A MULTIPLE-PRIORITY MEMORY SYSTEM FOR REAL-TIME MULTIPROCESSING

[75] Inventors: William K. Zuravleff, Mountainview;

Mark Semmelmeyer, Sunnyvale;
Timothy Robinson, Boulder Creek;
Scott Furman, Union City, all of Calif.

[73] Assignee: Microunity Systems Engineering, Inc.,

Sunnyvale, Calif.

[21] Appl. No.: 480,738
[22] Filed: Jun. 7, 1995

[51] Int. C I. 1101.1 13/00

[52] U.S. CI 395/308; 395/837; 395/838;

395/840; 395/859; 395/876

[58] Field of Search 395/306, 307,

395/308, 292, 309, 438, 441, 479, 468, 469, 470, 250, 840, 841, 842, 847, 849, 859, 861, 864, 863, 872, 874, 876

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Primary Examiner—Jack B. Harvey

Assistant Examiner—Raymond N. Phan

Attorney, Agent, or Firm—Burns, Doane, Swecker &

Mathis, L.L.P.

[57] ABSTRACT

A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

34 Claims, 9 Drawing Sheets