Assemblies and packages including die-to-die connections

(54) ASSEMBLIES AND PACKAGES INCLUDING DIE-TO-DIE CONNECTIONS

(75) Inventors: Eugene H. Cloud, Boise, ID (US);

Paul A. Farrar, South Burlington, VT
(US)

(73) Assignee: Micron Technology, Inc., Boise, ID
(US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

This patent is subject to a terminal disclaimer.

(21) Appl. No.: 10/382,025

(22) Filed: Mar. 5, 2003

(65) Prior Publication Data

US 2003/0160321 Al Aug. 28, 2003

Related U.S. Application Data

(60) Continuation ol application No. 09/944,487, filed on Aug. 30, 2001, which is a division ol application No. 09/615,009, filed on Jul. 12, 2000, now Pat. No. 6,525,413.

(51) Int. CI.7 H01L 23/02

(52) U.S. CI 257/686; 257/724; 257/777

(58) Field of Search 257/686, 693,

257/724, 777, 778, 779, 780, 781, 783, 787, 788, 789

(56) References Cited

U.S. PATENT DOCUMENTS

A semiconductor device assembly includes a first semiconductor die, such as a logic device, with bond pads arranged in an array on an active surface thereof, and at least one second semiconductor die, such as a memory device or an ancillary or parallel logic device, with bond pads on an active surface thereof with active surfaces thereof facing each other. Corresponding bond pads of the first and at least one second semiconductor dice are connected to each other by way of conductive structures disposed therebetween. The package includes the assembly and a carrier, such as a carrier substrate or leads. The first semiconductor die is oriented over the carrier such that bond pads thereof that are exposed beyond the periphery of each second semiconductor die face the carrier and are electrically connected to corresponding contacts thereof.

46 Claims, 7 Drawing Sheets