[56] References Cited
U.S. PATENT DOCUMENTS
3,820,078 6/1974 Curley et al 395/250
3,938,097 2/1976 Niguette, HI 395/425
4,268,907 5/1981 Porter et al 395/425
4,370,710 1/1983 Kroft 395/425
4,493,026 1/1985 Olnowich 395/425
4,504,902 3/1985 GaUaheretal 395/425
4,797,813 1/1989 Igarashi 395/425
4,811,209 3/1989 Rubinstein 395/425
4,819,154 4/1989 Stiffer et al 395/575
4.833.642 5/1989 Ooi 365/49
4,835,678 5/1989 Kofaj 395/425
4,905,188 2/1990 Chuang et al 395/425
4,914,582 4/1990 Bryg et al 395/425
4,920,478 4/1990 Furuya et al 395/425
4.970.643 11/1990 Cramm 395/400
5,043,886 8/1991 Witek et al 395/425
OTHER PUBLICATIONS
Nikkei Electronics, Nikkei-McGraw-Hill, Inc., Nov. 16, 1987, pp. 170-171.
Patterson, et al., Computer Architecture a Qualitative Approach, 1990, pp. 403-425, 454-474.
Primary Examiner—Thomas C. Lee
Assistant Examiner—Krisna Lim
Attorney, Agent, or Firm—Fay, Sharpe, Beall, Fagan,
Minnich & McKee
[57] ABSTRACT
In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
20 Claims, 5 Drawing Sheets
