Semiconductor assemblies, methods of forming structures over semiconductor ...

US006690046B2

(12) United States Patent (10) 1161661 N0.I US 6,690,046 B2 Beaman et al. (45) Date of Patent: Feb. 10, 2004

(54) SEMICONDUCTOR ASSEMBLIES, 5,378,645 A 1/1995 Inoue 6161. METHODS OF FORMING STRUCTURES 5,332,533 A 1/1995 Ahmed et elOVER SEMICONDUCTOR SUBSTRATES, 2 ett e1l~

, , 3. I C 3. . AND METHODS OF FORMING 5,464,792 A 11/1995 Tseng et al. TRANSISTORS ASSOCIATED WITH 5 500 380 A 3/1996 Kim SEMICONDUCTOR SUBSTRATES 575187946 A 5/1996 Kumda _ _ 5,596,218 A 1/1997 Soleimani et al. (75) Inventors: Kevin L. Beaman, Boise, ID (US); 576127558 A 3/1997 Harshfield Jehll T- Meere, Be1Se, ID (U5) 5,619,057 A 4/1997 i<6m616u 5,620,908 A 4/1997 Inoh et al. (73) Assignee: Micron Technology, Inc., Boise, ID 5,633,036 A 5/1997 Seebauer et al. <19 224111;: 1/122; , , ris ers e a .

( * ) Notice: Subject to any disclaimer, the term of this 5,635,949 A 11/1997 Yflshimfl

patent is extended or adjusted under 35 5>716>864 A 2/1998 Abe

(List continued on next page.)
OTHER PUBLICATIONS

Wolf, S., “Silicon Processing for the VLSI Era”, Lattice
Press 1990, vol. 2, pp. 212-213.

(List continued on next page.)

Primary Examiner—David Nelms
Assistant Examiner—David Nhu
(74) Attorney, Agent, or Firm—Wells St. John P.S.

(57) ABSTRACT

The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. Afirst oxide region is on the substrate and covers the first region of the substrate. The first oxide region has nitrogen provided therein and substantially all of the nitrogen is at least 10 A above the semiconductor substrate. A first conductive layer is over the first oxide region and defines a first transistor gate. First source/drain regions are proximate the first transistor gate and gatedly connected to one another by the first transistor gate. The second region is covered by a second oxide region. Asecond conductive layer is over the second oxide region and defines a second transistor gate. Second source/drain regions are proximate the second transistor gate and gatedly connected to one another by the second transistor gate.

5 Claims, 5 Drawing Sheets

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U.S. PATENT DOCUMENTS 6,228,701 5/2001 Dehm et al.
6 232 244 5 2001 Ibok

5,719,083 A 2/1998 Komfltsu 6:255:703 7I2001 Hause et al. ......... .. 257/382 5,760,475 A 6/ 1998 Cronin 6,268,296 7/2001 Misium et al.

5,763,922 A 6/1998 C1196 6,274,442 8/2001 Gardner et al. ...... .. 438/287 5,834,372 A 11/1998 L66 6,297,162 10/2001 Jang etal.

5,837,592 A 11/1998 Chang 6161 6,399,448 6/2002 Mukhopadhyay et al.

5,837,598 A 11/1998 Aronowitz et al. 6,410,991 6/2002 Kawai ct a1_

5,840,610 A 11/1998 Gilmer et al. 6,413,881 7/2002 Amnowitz ct a1_

5,861,651 A 1/1999 Brasen et al. ............. .. 257/411 674367771 8/2002 jang ct a1_

5,939,750 A 8/1999 Early 6,450,116 9/2002 Noble etal.

5,960,289 A 9/1999 Tsui et al. 674827690 11/2002 Shibata

5,960,302 A 9/1999 Ma 61 61- 6,492,690 12/2002 UCHO et al.

5,972,783 A 10/1999 Awi91a1~ 2003/0034518 2/2003 Yoshikawa

5,994,749 A 11/1999 Oda

5,998,253 A 12/1999 Loh et al. OTHER PUBLICATIONS

6,033,998 A 3/2000 Aronowitz et al. “ _ _ _ 1, _ 670547396 A 4/2000 D0211 Wolf, S., Silicon Processing for the VLSI Era , Lattice 610571220 A 5/2000 Ajmera ct a1_ Press 1990, vol. 2, pp. 188-189, 194-195, 609-614. 6,080,682 A 7/2000 Ibok Ko, L. et al., “The Effect of Nitrogen Incorporation into the 6,087,229 A 7/2000 Ar0n0WitZ et a1, Gate Oxide by Using Shallow Implantation of Nitrogen and 6,091,109 A 7/2000 H086/gawa Drive-In Process”, IEEE 1996, pp. 32-35.

6>991>119 A 7/2999 H9499‘? ct ‘IL Doyle, B. et al., “Simultaneous Growth of Different Thick°’993’°°1 A 7/2999 Tnvedl °t °l' ness Gate Oxides in Silicon CMOS Processing”, IEEE vol. 6,110,780 A 8/2000 YLI et al. 16 7) J 1 1995 301_302

6,110,842 A 8/2000 Okuno et al. ( 2 “" PP" " , , 671147203 A 9/2000 Ghidini ct a1_ Kuroi, T. al., The Effects of Nitrogen Implantation Into 671367636 A 10/2000 Wu €+Poly-Silicp]iLS(I}alt_e 11130111 G21I]k5~OX1CI€f 1;_‘I"OI;1€I"I1€T”l,) 1994 611401137 A 10/2000 Degusk ct a1_ ympos. on ec no ogy igest o ec nica apers, 6,174,821 B1 1/2001 Doan IEEE 1994, pp. 107-108.

6,184,110 B1 * 2/2001 Ono et a1, ---------------- -- 438/513 Liu, C.T. et al., “Multiple Gate Oxide Thickness for 2GHz 0,197,701 B1 3/2001 S1106 61 81~ System-on-a-Chip Technologies”, IEEE 1998, pp. 6,207,532 B1 3/2001 Lin et al. 589_592_

6,207,586 B1 3/2001 Ma et al.

6,225,167 B1 5/2001 Yu et al. * cited by examiner

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