Phase detector for very high frequency clock and data recovery circuits

United States Patent [19]

Wong et al.

[54] PHASE DETECTOR FOR VERY HIGH FREQUENCY CLOCK AND DATA RECOVERY CIRCUITS

[75] Inventors: Hee Wong; Tsun-Kit Chin, both of San Jose, Calif.

[73] Assignee: National Semiconductor, Santa Clara, Calif.

[21] Appl. No.: 26,266

[22] Filed: Mar. 4,1993

Related U.S. Application Data

[63] Continuation of Ser. No. 730,228, Jul. 15, 1991, abandoned.

[51] Int. CI.' H03D 3/20

[52] U.S. CI 375/119; 375/120;

307/511; 328/155

[58] Field of Search 375/81-83,

375/119, 120; 328/109, 111, 133, 134; 329/307, 309, 310; 307/511, 514, 516, 518, 234, 118;

331/1 R, 11-12, 25, 1 A

[56] References Cited

U.S. PATENT DOCUMENTS

4,527,277 7/1985 Kosaka et al 328/133

4,584,695 4/1986 Wong et al 375/81

4,635,277 1/1987 Blake et al 375/119

4,751,469 6/1988 Nakagawa et al 328/133

4,940,948 7/1990 Laws et al 329/307

5,003,562 3/1991 Van Driest et al 375/81

5,117,135 5/1992 Lee et al 328/133

5,126,602 6/1992 Lee et al 328/133

MM I I I I i II i II I t Ul l II II li I li III II l Lil Mil,

US005329559A

[li] Patent Number: 5,329,559 [45] Date of Patent: Jul. 12,1994

Primary Examiner—Stephen Chin

Assistant Examiner—Young Tse

Attorney, Agent, or Firm—Flehr, Hohbach, Test,

Albritton & Herbert

[57] ABSTRACT

A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery. In the preferred embodiment, the pulse signals from one positive and one negative data transition are integrated or averaged so as to eliminate problems associated with any duty cycle distortion and/or jitter in the incoming data stream. The sign and magnitude of the difference in the widths of the averaged pulse signals are proportional to the average phase error between the incoming data signal and the PLL clock signal.

14 Claims, 7 Drawing Sheets