Planarization of metal films for multilevel interconnects

United States Patent [i9]

Tuckerman

[11] Patent Number: 4,681,795 [45] Date of Patent: Jul. 21, 1987

[54] PLANARIZATION OF METAL FILMS FOR MULTILEVEL INTERCONNECTS

[75] Inventor: David B. Tuckerman, Livermore, Calif.

[73] Assignee: The United States of America as represented by the Department of Energy, Washington, D.C.

[21] Appl. No.: 768,590

[22] Filed: Aug. 23, 1985

Related U.S. Application Data

[63] Continuation-in-part of Ser. No. 748,375, Jun. 24, 1985.

[51] Int. CI.* B32B 3/00; H01L 21/00;

H01L 21/04; B05D 3/06

[52] U.S. CI 428/209; 428/901;

29/571; 29/576 B; 141/1.5; 141/187; 427/53.1;

427/94

[58] Field of Search 29/571, 576 B, 578,

29/591; 141/1.5, 187; 427/53.1, 86, 89, 90, 93, 94, 96; 428/209, 901

[56] References Cited

U.S. PATENT DOCUMENTS

4,214,918 7/1980 Gat et al 148/1.5

4,249,960 2/1981 Schnable et al 148/1.5

4,258,078 3/1981 Celler et al 427/43.1

4,259,367 3/1981 Dougherty, Jr 427/96

4,284,659 8/1981 Jaccodine et al 427/53.1

4,305,973 12/1981 Yaron et al 427/35

4,327,477 5/1982 Yaron et al 29/576 B

4,395,433 7/1983 Nagakubo et al 427/35

4,396,458 8/1983 Platter et al 156/643

4,495,255 1/1985 Draper et al 428/669

4,541,169 9/1985 Bartush 29/591

4,555,301 11/1985 Gibson et al 156/617 R

4,555,843 12/1985 Mahli 29/571

4,561,906 12/1985 Calder et al 148/1.5

4,596,604 6/1986 Akiyama et al 148/1.5

4,601,939 7/1986 Gats et al 428/161

OTHER PUBLICATIONS

Raffel et al, IEEE-IEDIM Tech. Digest, 1980 p. 132. Sirkin et al, J. Electrochem Soc. 131, (1984) p. 123.

Primary Examiner—John E. Kittle

Assistant Examiner—Patrick J. Ryan

Attorney, Agent, or Firm—Henry P. Sartorio; L. E.

Carnahan; Judson R. Hightower

[57] ABSTRACT

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

20 Claims, 8 Drawing Figures