Brevet US6085314 - Central processing unit including APX and DSP cores and including selectable ...

United States Patent [w]

Asghar et al.

US006085314A [ii] Patent Number: [45] Date of Patent:

6,085,314 *Jul. 4,2000

[54] CENTRAL PROCESSING UNIT INCLUDING APX AND DSP CORES AND INCLUDING SELECTABLE APX AND DSP EXECUTION MODES

[75] Inventors: Saf Asghar, Austin, Tex.; Andrew Mills, Coto-de-Caza, Calif.

[73] Assignee: Advnced Micro Devices, Inc.,

Sunnyvale, Calif.

[ * ] Notice: This patent is subject to a terminal disclaimer.

[21] Appl. No.: 08/969,858 [22] Filed: Nov. 14, 1997

Related U.S. Application Data

[63] Continuation-in-part of application No. 08/618,243, Mar. 18, 1996, Pat. No. 5,794,068.

[51] Int. CI.7 G06F 9/30; G06F 15/163

[52] U.S. CI 712/213; 712/23; 712/35;

712/207

[58] Field of Search 395/800.23, 800.35,

395/383, 387, 359, 800.75; 712/23, 35, 204, 206, 213, 207, 203, 208, 210, 211, 217, 230, 245

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.

20 Claims, 11 Drawing Sheets