[54] SIGNAL LINE TERMINAL ALLOCATION METHOD
[75] Inventors: Yoshinori Nishiyama, Odawara;
Tomoatsu Yanagita, Ebina; Masahiko
Nagai, Kanagawa; Mitsuru
Morikuni, Ebina; Kenji Matsumoto,
Kanagawa, all of Japan
[73] Assignees: Hitachi, Ltd., Tokyo; Hitachi
Computer Engineering Co., Ltd.,
Kanagawa, both of Japan
[21] Appl. No.: 472,816
[22] Filed: Jan. 31, 1990
[30] Foreign Application Priority Data
Feb. 6, 1989 [JP] Japan 1-025785
[51] Int. CI.' G06F 15/20
[52] U.S. CI 364/490; 364/488;
364/491
[58] Field of Search 364/488, 489, 490, 491
[56] References Cited
U.S. PATENT DOCUMENTS
5,046,017 9/1991 Yuyama et al 364/491
5,072,402 12/1991 Ashtaputre et al 364/490
Primary Examiner—Parshotam S. Lall
Assistant Examiner—Edward R. Cosimano
Attorney, Agent, or Firm—Antonelli, Terry, Stout &
Kraus
[57] ABSTRACT
A signal line terminal allocation method includes an electronic device which is hierarchically designed to obtain terminal allocations which satisfy electrical restrictive conditions. The electronic device includes high hierarchial components and low hierarchial components; the high hierarchial components are connected to the low hierarchical components by a plurality of signal lines through a plurality of signal line terminals. The method including the steps of: 1) obtaining all the different combinations of an allocation of the signal lines to the signal line terminals; 2) calculating a plurality of signal line lengths for all the different combinations, each of the plurality of signal line lengths corresponding to a sum of the line lengths of each of the signal lines in the allocation; and 3) selecting the combinations of allocation of signal lines in which electrical restrictions corresponding to each of the plurality of signal lines are satisfied, the electrical restrictions including the maximum line length. The above method includes groups of plural signal lines of both high and low hierarchial components.
7 Claims, 5 Drawing Sheets
