United States Patent [w]
McDermott et al.
US005926053A [ii] Patent Number: 5,926,053 [45] Date of Patent: Jul. 20,1999
[54] SELECTABLE CLOCK GENERATION MODE
[75] Inventors: Mark W. McDermott, Austin, Tex.;
Antone L. Fourcroy, Fort Collins,
Colo.
[73] Assignee: National Semiconductor Corporation,
Santa Clara, Calif.
[21] Appl. No.: 08/572,813 [22] Filed: Dec. 15, 1995
[51] Int. CI. G06F 1/06
[52] U.S. CI 327/298; 327/291; 327/150;
327/159; 395/556; 395/558
[58] Field of Search 327/291, 298,
327/147, 149, 150, 153, 156, 158, 159, 161; 395/556, 558
[56] References Cited
U.S. PATENT DOCUMENTS
4,933,955 6/1990 Warren et al 331/49
4,982,116 1/1991 Lee 327/298
5,142,247 8/1992 Lada, Jr. et al 331/49
5,155,840 10/1992 Niijima 395/530
5,184,350 2/1993 Dara 370/105.3
5,233,314 8/1993 McDermott et al 331/17
5,336,939 8/1994 Eitrheim et al 307/269
5,357,146 10/1994 Heimann 327/298
5,359,232 10/1994 Eitrheim et al 307/268
5,373,254 12/1994 Nakauchi et al 331/49
5,428,622 6/1995 Kuban et al 371/223
5,475,324 12/1995 Tomiyori 327/99
5,483,185 1/1996 Scriber et al 329/99
FOREIGN PATENT DOCUMENTS
248836 2/1990 Japan 327/99
3238913 10/1991 Japan 327/99
5268020 10/1993 Japan 327/99
Primary Examiner—Tuan T. Lan
Attorney, Agent, or Firm—-John L. Maxin
[57] ABSTRACT
A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
14 Claims, 18 Drawing Sheets
