[54] METHOD OF MOUNTING AN ELECTRONIC PART WITH BUMPS ON A CIRCUIT BOARD
[75] Inventors: Shoji Sakemi, Fukuoka; Yoshiyuki Wada, Onojo, both of Japan
[73] Assignee: Matsushita Electric Industrial Co.,
Ltd., Osaka, Japan
[21] Appl. No.: 457,805
[22] Filed: Jun. 1,1995
Related U.S. Application Data
[63] Continuation of Ser. No. 205,630, Mar. 4,1994, abandoned.
[30] Foreign Application Priority Data
Mar. 11, 1993 [JP] Japan 5-050464
Jan. 18, 1994 [JP] Japan 6-003469
[51] Int. CI.6 H05K 1/14
[52] U.S. CI 174/261; 174/260; 174/266;
361/767; 361/768; 361/760; 29/832; 29/833;
29/840
[58] Field of Search 361/778, 777,
361/774, 767, 768, 760, 808; 174/262, 266, 260, 261; 29/832, 833, 834, 840
[56] References Cited
U.S. PATENT DOCUMENTS 5,011,066 4/1991 Thompson 228/180.2
5,192,835 3/1993 Bull et al 174/260
5,233,504 8/1993 Mellon et al 361/760
5,266,749 11/1993 Kawakami et al 174/262
5,329,423 7/1994 Scholz 361/760
FOREIGN PATENT DOCUMENTS 2105420 4/1990 Japan .
Primary Examiner—Laura Thomas
Attorney, Agent, or Firm—Stevens, Davis, Miller & Mosher
[57] ABSTRACT
A method of mounting an electronic part with bumps on a circuit board is disclosed which enables bumps to be bonded to electrodes of the circuit board with certainty and which enables the judgement of the quality of bonding with precision. By making an area of the electrodes of the circuit board larger than those of the electrodes of the electronic part, the bumps heated and molten in the reflow soldering are spread over the electrodes of the circuit board to make its vertical cross-sectional configuration in a trapezoidal form. Therefore, the height dispersion of the bumps and the curvature of the circuit board are effectively absorbed whereby all the bumps can be bonded to the electrodes of the circuit board. Further, by measuring the planar area of the bumps, the judgement of the quality of bonding can be made with precision.
