Method and circuitry for enabling internal test operations in a VLSI chip

[54] METHOD AND CIRCUITRY FOR ENABLING INTERNAL TEST OPERATIONS IN A VLSI CHIP

[75] Inventors: Haluk Katircioglu, Irvine; John A.

De Beule, Rancho Santa Margarita;
Debaditya Mukherjee, El Toro, all of
Calif.

[73] Assignee: Unisys Corporation, Blue Bell, Pa.
[21] Appl. No.: 364,412
[22] Filed: Jun. 12,1989

[51] Int. CL* G01R 31/28

[52] U.S. a 365/201; 371/21.2;

371/22.4; 371/22.5

[58] Field of Search 324/73 R, 73 AT;

371/21.1, 21.2, 21.3, 21.4, 22.1, 22.5, 25.1;

365/201

[56] References Cited

U.S. PATENT DOCUMENTS

4,701,920 10/1987 Resnick et al 324/73 R

4,764,926 8/1988 Knight et al 371/22.5

4,768,196 8/1988 Jou et al 371/22.4

4,827,476 5/1989 Garcia 371/21.1

Primary Examiner—Ernest F. Karlsen

Attorney, Agent, or Firm—Alfred W. Kozak; Nathan

Cass; Robert S. Bramson

[57] ABSTRACT

A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunction shift " registers (MFSR's) which operate as flip-flops during a test cycle and as latches during normal operations. Selected MFSR's function to generate test patterns to the chip circuitry which have output signals to an output MFSR which collects a signature that can be compared to a predetermined signature to determine error-free or error-incurred operation of the VLSI circuitry.

10 Claims, 28 Drawing Sheets