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US006868531B1
(12) United States Patent ao) Patent No.: us 6,868,531 Bi
Hovanetz (45) Date of Patent: Mar. 15,2005
(54) GENERATION OF ORDERED
INTERCONNECT OUTPUT FROM AN HDL
REPRESENTATION OF A CIRCUIT
(75) Inventor: Cory J. Hovanetz, Brooklyn Center,
MN (US)
(73) Assignee: Unisys Corporation, Blue Bell, PA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 31 days.
(21) Appl. No.: 10/330,984
(22) Filed: Dec. 27, 2002
(51) Int. CI.7 G06F 17/50
(52) U.S. CI 716/1; 716/12
(58) Field of Search 716/1, 12; 371/23;
364/488
(56) References Cited
U.S. PATENT DOCUMENTS
5,425,036 A * 6/1995 Liu et al 714/735
5,898,705 A * 4/1999 Graef 714/738
6,539,534 Bl * 3/2003 Bennett 716/17
6,684,376 Bl * 1/2004 Kerzman et al 716/8
6,701,289 Bl * 3/2004 Garnett et al 703/14
Techniques are described for generating and presenting interconnection information for a circuit in a manner that allows a designer to more easily validate the interconnectivity of the circuit. For example, a system comprises a computer-readable medium to store data that defines a circuit in accordance with a hardware description language. An interconnect analysis module processes the data to identify instances of circuit components having interconnects, and any signals coupled to the interconnects. The output includes an ordered representation of the interconnects, and specifies for each interconnect a respective signal associated with the interconnect and the other interconnects coupled to the signal. The output may be arranged to order the representation based on page numbers of schematic diagrams with which the instances are associated. The interconnect analysis module may generate the output in a two-dimensional format having rows and columns suitable for display in a spreadsheet application.
34 Claims, 4 Drawing Sheets
