Vertically integrated semiconductor package for an implantable medical device

United States Patent

Weinberg et al.

[19]

US006014586A [ii] Patent Number: [45] Date of Patent:

6,014,586 Jan. 11,2000

[54] VERTICALLY INTEGRATED

SEMICONDUCTOR PACKAGE FOR AN
IMPLANTABLE MEDICAL DEVICE

[75] Inventors: Alvin H. Weinberg, Moorpark; Buehl E. Truex, Glendora, both of Calif.

[73] Assignee: Pacesetter, Inc.

[21] Appl. No.: 08/806,364 [22] Filed: Feb. 27, 1997

Related U.S. Application Data

[63] Continuation of application No. 08/560,920, Nov. 20, 1995, abandoned.

[51] Int. C I. A61N 1/372

[52] U.S. C I 607 36

[58] Field of Search 607/36, 37; 257/686,

257/777, 786, 784, 723, 724; 361/735, 760, 783, 813, 820, 777

[56] References Cited

U.S. PATENT DOCUMENTS

5,470,345 11/1995 Hassler et al 607/36

5,473,198 12/1995 Hajiyz et al 257/786

FOREIGN PATENT DOCUMENTS

9215368 9/1992 European Pat. Off 607/36

58-92230 6/1983 lapan .

60-182731 9/1985 lapan .

63-128736 6/1988 lapan .

3-169062 7/1991 lapan .

4- 56262 2/1992 lapan 257/686

5- 13663 1/1993 lapan 257/777

OTHER PUBLICATIONS

Tuckerman, D.B., et al., "Laminated Memory: A New 3-Dimensional Packaging Technology for MCMs," IEEE, pp. 58-63, (Jul. 1994).

"8 Megabit High Speed CMOS SRAM (DPS512X16MKn3), " Dense-Pac Microsystems, pp. 1-8, Revision D, (No date).

Primary Examiner—-William E. Kamm
Assistant Examiner—George R. Evanisko

[57] ABSTRACT

An electronic package having vertically integrated components placed upon a substrate surface is configured to increase packing density of the components. Integrated circuits which are vertically-stacked and attached to the substrate surface communicate with surrounding components through connection to bond pads on the substrate surface. The bond pads can be placed entirely about a perimeter of the integrated circuits to achieve optimal packing density. Individual bond pads may be shared by two or more integrated circuits by connection therewith. In an alternative embodiment, a separate integrated circuit is attached to the substrate adjacent to the stacked integrated circuits with a row of shared bond pads positioned therebetween. Individual passive or active components may be placed between bond pads for incorporation into the circuit structure.

18 Claims, 4 Drawing Sheets

55 JO