US005749084A [11] Patent Number: [45] Date of Patent:
[54] ADDRESS GENERATION UNIT WITH SEGMENTED ADDRESSES IN A MICROPROCESSOR
[75] Inventors: Kamla P. Buck, Portland; Scott D. Rodgers; Andrew F. Glew, both of
Hillsboro, all of Oreg.
[73] Assignee: Intel Corporation, Santa Clara, Calif.
[ * ] Notice: The term of this patent shall not extend
beyond the expiration date of Pat. No.
5,590,297.
[21] Appl. No.: 634,092
[22] Filed: Apr. 17,1996
Related U.S. Application Data
[63] Continuation of Ser. No. 176,066, Jan. 4, 1994, Pat No. 5,590,297.
[51] Int. Cl.6 G06F 12/02: G06F 12/06;
G06F 12/10
[52] U.S. Cl 711/1; 711/100; 711/3;
711/206; 711/200
[58] Field of Search 395/401, 420,
395/415, 417, 418, 419, 421.07, 421.1,
653, 490, 570, 800; 365/49
A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
25 Claims, 4 Drawing Sheets
