[54] METHOD FOR CONTROL OF RANDOM TEST VECTOR GENERATION
[75] Inventors: Paul M. Kinzelman, Hudson; Nicholas A. Warchol, Boxborough, both of Mass.
[73] Assignee: Digital Equipment Corporation, Maynard, Mass.
[21] Appl. No.: 345,271
[22] Filed: Nov. 28, 1994
Related U.S. Application Data
[63] Continuation of Ser. No. 40,796, Mar. 31,1993, abandoned.
[51] Int. CI.6 G06F 11/00
[52] U.S. CI 371/27; 371/51.1; 371/25.1;
364/578; 395/920; 395/183.01
[58] Field of Search 371/27, 16.1, 51.1,
371/25.1; 395/275, 575, 183.1; 364/578, 488, 489, 490
[56] References Cited
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OTHER PUBLICATIONS
Ulrich E., "Serial/parallel event scheduling for the simulation of large systems";Preceeding-1968 ACM National Coference 1968.
Menzel et al.; "A multi-level simulation system for MOS VLSI networks"; IEEE 1989 Feb. 1989.
Primary Examiner—Ellis B. Ramirez
Assistant Examiner—Kamini S. Shah
Attorney, Agent, or Firm—Lindsay G. McGuinness; Denis
G. Maloney; Arthur W. Fisher
[57] ABSTRACT
A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.
8 Claims, 6 Drawing Sheets
