(54) ELECTROSTATIC DISCHARGE
PROTECTION DEVICE INCLUDING
PRECHARGE REDUCTION
(75) Inventors: Charvaka Duwury, Piano, TX (US);
Chih-Ming Hung, McKinney, TX (US)
(73) Assignee: Texas Instruments Incorporated,
Dallas, TX (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 221 days.
(21) Appl. No.: 10/944,299
(22) Filed: Sep. 17, 2004
(65) Prior Publication Data
US 2006/0061929 Al Mar. 23, 2006
(51) Int. CI.
H02H 9/00 (2006.01)
(52) U.S. CI 361/56; 361/91.1; 361/111;
361/118; 257/355
(58) Field of Classification Search 361/56,
361/91.1, 111, 118; 257/355 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
3,806,829 A * 4/1974 Duston et al 372/38.01
ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor (811), preferably about 10 kQ, connected to the discharge circuit, and a control MOS transistor (812) in series with the discharge resistor. The transistor source (812a) is connected to the resistor, the drain (8126) to ground, and the gate (812c) to core power (813) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.
10 Claims, 4 Drawing Sheets
