[54] SEMICONDUCTOR MEMORY DEVICE
WITH CACHE MEMORY ADDRESSABLE BY
BLOCK WITHIN EACH COLUMN
[75] Inventors: Kazuyasu Fujishima; Hideto Hidaka;
Mikio Asakura; Yoshio Matsuda, all of Hyogo, Japan
[73] Assignee: Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan
[21] Appl. No.: 228,589
[22] Filed: Aug. 5,1988
[30] Foreign Application Priority Data
Aug. 5, 1987 [JP] Japan 62-196823
[51] Int. CI.* G11C 7/00
[52] U.S. CI 365/230.03; 365/240;
365/230.08
[58] Field of Search 365/189.05, 230.03,
365/230.08, 240, 238-239
[56] References Cited
U.S. PATENT DOCUMENTS
4,330,852 5/1982 Redwine et al 365/221 X
4,577,293 3/1986 Matick et al 365/189 X
4,725,945 2/1988 Kronstadt et al 365/230.03
4,755,974 7/1988 Yamada et al 365/230.03
4,803,621 2/1989 Kelly 365/230.03
FOREIGN PATENT DOCUMENTS
0167089 1/1986 European Pat. Off. 365/230.03
0595481 1/1984 Japan 365/230.03
Primary Examiner—Stuart N. Hecker
Assistant Examiner—Alfonso Garcia
Attorney, Agent, or Firm—Lowe, Price, LeBlanc,
Becker .& Shur
[57] ABSTRACT
A semiconductor memory includes a memory cell array
having a plurality of bit lines and a plurality of word
lines arranged intersecting with the bit lines. A plurality
of memory cells are arranged at intersections of the bit
lines and the word lines, respectively. Word line select-
ing circuitry selects one of the word lines responsive to
a row address and reads out to each of the bit lines
information stored in the memory cell associated with
the selected word line. A plurality of sense amplifiers
are associated with corresponding rows of the memory
for detecting and amplifying the information stored in
respective memory cells. A first column selector circuit
selects the sense amplifiers corresponding to a column
address when the column address is applied and reads
information held in the sense amplifier. Blocks are
formed by dividing the memory cell array into groups
of bit lines, each of the groups comprising a predeter-
mined number of bit lines with block information trans-
ferred simultaneously from corresponding ones of the
groups of bit lines of a selected block when the column
address corresponding to the selected block is applied.
Data registers hold information of an associated block.
A second column selector reads data corresponding to
the column address from the data register when the
column address is applied.
7 Claims, 9 Drawing Sheets
