(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2003/0002355 Al
Janzen et al. (43) Pub. Date: Jan. 2,2003
(76) Inventors: Jeffery W. Janzen, Meridian, ID (US);
Troy A. Manning, Meridian, ID (US);
Chris G. Martin, Boise, ID (US);
Brent Keeth, Boise, ID (US)
Correspondence Address:
DICKSTEIN SHAPIRO MORIN & OSHINSKY
LLP
2101 L STREET NW
WASHINGTON, DC 20037-1526 (US)
(21) Appl. No.: 10/222,798
(22) Filed: Aug. 19, 2002
Related U.S. Application Data
(62) Division of application No. 09/790,538, filed on Feb. 23, 2001, now Pat. No. 6,445,624.
Publication Classification
(51) Int. CI.7 G11C 7/00
(52) U.S. C I 365/191
(57) ABSTRACT
The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
