Apparatus and method for compressing redundancy information for embedded ...

inn iiiiiii Hi mi mi ij||jp JJJPJP ^ ^ ^ ^ ^

(12) United States Patent

Gross

(io) Patent No.: (45) Date of Patent:

US 7,162,669 B2 Jan. 9, 2007

(54) APPARATUS AND METHOD FOR
COMPRESSING REDUNDANCY
INFORMATION FOR EMBEDDED
MEMORIES, INCLUDING CACHE
MEMORIES, OF INTEGRATED CIRCUITS

(75) Inventor: Fred Gross, Fort Collins, CO (US)

(73) Assignee: Hewlett-Packard Development

Company, L.P., Houston, TX (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 428 days.

(21) Appl. No.: 10/458,474

(22) Filed: Jun. 10, 2003

(65) Prior Publication Data

US 2004/0255209 Al Dec. 16, 2004

(51) Int. CI.

G11C 29/00 (2006.01)

(52) U.S. CI 714/710; 714/7; 714/25;

714/723; 365/201

Field of Classification Search None

See application file for complete search history.

(58) (56)

References Cited

U.S. PATENT DOCUMENTS 6,768,694 Bl * 7/2004 Anand et al 365/225.7

6,842,874 Bl * 1/2005 Voshell 714/723

2001/0028588 Al* 10/2001 Yamada et al 365/210

2004/0153900 Al* 8/2004 Adams et al 714/710

2005/0030822 Al * 2/2005 Beer 365/232

OTHER PUBLICATIONS

Mazumder et al., "A Novel Built-in Self-Repair Approach to VLSI Memory Yield Enhancement", IEEE International Test Conference 1990, pp. 833-841.*

Cowan et al., "On-Chip Repair and an ATE Independent Fusing Methodology", IEEE International Test Conference 2002, Oct. 7-10, 2002, pp. 178-186 *

Ouellette et al., "Shared Fuse Macros for Multiple Embedded
Memory Devices with Redundancy", IEEE Conference on Custom
Integrated Circuits, May 6-9, 2001, pp. 191-194*
Handy, "The Cache Memory Book", Academic Press, Second
Edition, pp. xii-xiii, 14-23, 46-47, 54-57, 60-65, 74-75.*

* cited by examiner

Primary Examiner—Albert Decady
Assistant Examiner—John P. Trimmings