(54) APPARATUS AND METHOD FOR MATRIX MEMORY SWITCHING ELEMENT
(75) Inventors: John Mick, Alpine, AZ (US); Craig Lindahl, McKinney, TX (US); Yongdong Zhao, Pleasanton, CA (US)
(73) Assignee: Integrated Device Technology, Inc.,
San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 1295 days.
This patent is subject to a terminal disclaimer.
(21) Appl.No.: 11/185,072
(22) Filed: Jul. 19, 2005
(65) Prior Publication Data
US 2005/0254330 Al Nov. 17, 2005
Related U.S. Application Data
(63) Continuation-in-part of application No. 10/037,433, filed on Jan. 3, 2002, now Pat. No. 7,020,133.
(51) Int. CI.
H04L12/56 (2006.01)
(52) U.S. CI 370/371; 370/370; 370/413;
370/414; 370/235
(58) Field of Classification Search 370/371,
370/235; 365/189.05; 712/15 See application file for complete search history.
A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.
24 Claims, 20 Drawing Sheets
