United States Patent [w]
Yamamoto
US005925931A [ii] Patent Number: [45] Date of Patent:
[54] SEMICONDUCTOR DEVICE HAVING
INTERCONNECT LINES AND CONNECTION
ELECTRODES FORMED IN GROOVE
PORTIONS OF AN INSULATING LAYER
[75] Inventor: Mitsuhiko Yamamoto, Akishima, Japan
[73] Assignee: Casio Computer Co., Ltd., Tokyo, Japan
[21] Appl. No.: 08/956,140
[22] Filed: Oct. 22, 1997
[30] Foreign Application Priority Data
Oct. 31, 1996 [JP] Japan 8-304193
[51] Int. CI.6 H01L 23/528; H01L 23/48;
H01L 23/52
[52] U.S. CI 257/737; 257/738; 257/784;
257/786; 257/758; 257/778; 257/780
[58] Field of Search 257/737, 738,
257/734, 758, 690, 692, 693, 697, 698, 700, 778-780, 784, 786
[56] References Cited
U.S. PATENT DOCUMENTS
4,720,738 1/1988 Simmons 257/738
4,984,061 1/1991 Matsumoto 257/786
5.394,013 2/1995 Oku et al 257/78
5,604,379 2/1997 Mori 257/737
5,661,344 8/1997 Havemann et al 257/758
5,719,439 2/1998 Iwasaki et al 257/786
5.757,078 5/1998 Matsuda et al 257/738
5,801,446 9/1998 DiStelano et al 257/778
FOREIGN PATENT DOCUMENTS
55-78549 6/1980 Japan 257/737
58-200526 11/1983 Japan 257/737
63-78555 4/1988 Japan 257/737
2-260425 10/1990 Japan 257/758
Primary Examiner—Alexander Oscar Williams
Attorney, Agent, or Firm—Frishaul, Holtz, Goodman,
Langer & Chick, PC.
[57] ABSTRACT
A semiconductor chip has such a structure as to have first connection electrodes formed at its upper circumlerential edge portion and each exposed over a corresponding opening in a protective layer. An insulating layer is formed on the semiconductor chip except at each opening in the protective layer. Interconnect lines ol an electroless-plated layer are formed on the first connection electrode. Solder bumps are formed on second connection electrodes formed together with the interconnect lines.
13 Claims, 21 Drawing Sheets
