Brevet US6021265 - Interoperability with multiple instruction sets

[21] Appl. No.: 08/840,557 [22] Filed: Apr. 14, 1997

Related U.S. Application Data

[62] Division of application No. 08/477,781, Jun. 7, 1995, Pat. No. 5,758,115.

[30] Foreign Application Priority Data

Jun. 10, 1994 [GB] United Kingdom 9411670

[51] Int. CI.7 G06F 9/30

[52] U.S. CI 395/385; 395/386

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Primary Examiner—Robert B. Harrell
Assistant Examiner—Kenneth R. Coulter
Attorney, Agent, or Firm—Fenwick & West LLP

Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.

14 Claims, 3 Drawing Sheets