United States Patent 
MacWilliams et al.
 CACHE MEMORY INTEGRATED CIRCUIT FOR USE WITH A SYNCHRONOUS CENTRAL PROCESSOR BUS AND AN ASYNCHRONOUS MEMORY BUS
 Inventors: Peter D. MacWilliams; Clair C.
Webb, both of Aloha; Robert L.
Farrell, Portland, all of Oreg.
 Assignee: Intel Corporation, Santa Clara, Calif.
 Appl. No.: 710,075
 Filed: Jun. 4, 1991
 Int. a.' G06F 12/08; G06F 12/28
 U.S. a 395/425; 364/DIG. 1;
364/DIG. 2; 364/238.6; 364/239.51; 364/243.4  Field of Search ... 364/200 MS File, 900 MS File;
395/400 MS, 425 MS
 References Cited
U.S. PATENT DOCUMENTS
4,442,487 4/1984 Fletcher et al 395/425
4,467,411 8/1984 Fry et al 395/395
4,905,188 2/1990 Chuang et al 395/425
5,003,465 3/1991 Chisholm et al 395/275
5,025,366 6/1991 Baror 395/425
5,091,846 2/1992 Sachs et al 395/250
[ii] Patent Number: 5,228,134  Date of Patent: Jul. 13, 1993
5,119,485 6/1992 Ledbetter, Jr. et al 395/425
5,125,084 1/1992 Begun et al 395/375
Primary Examiner—Joseph L. Dixon
Assistant Examiner—keba I. Elmore
An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, writebacks and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
27 Claims, 37 Drawing Sheets
CPU CONTROLS CLK (ADS#,W/R*,HITM#,BOFF#)
-M- - --Azi-r—
TIMING K I [ OE.LE.WAY J I/Q DR',VERS 1^-23
(FROM MEMORY BUS CONTROLLER)
2X.4X.8X MEMORY DATA (TO/FROM MEMORY BUS)