Method for producing ultra-fine interconnection features

United States Patent

[19]

Lin

US005863707A [ii] Patent Number: 5,863,707 [45] Date of Patent: Jan. 26, 1999

[54] METHOD FOR PRODUCING ULTRA-FINE INTERCONNECTION FEATURES

[75] Inventor: Ming-Ren Lin, Cupertino, Calif.

[73] Assignee: Advanced Micro Devices, Inc.,

Sunnyvale, Calif.

[21] Appl. No.: 798,992

[22] Filed: Feb. 11, 1997

[51] Int. CI.6 G03C 5/00

[52] U.S. CI 430/313; 430/317; 430/318

[58] Field of Search 430/313, 322,

430/325, 317, 318, 312, 430

[56] References Cited

U.S. PATENT DOCUMENTS

4,641,420 2/1987 Lee 29/511

4,944,836 7/1990 Beyer et al 156/645

4,965,226 10/1990 Gootzen et al 437/189

5,093,279 3/1992 Aiidreshak et al 457/173

5,096,849 3/1992 Beilstein, Ir. et al 437/67

5,198,693 3/1993 Imken et al 257/720

5,262,354 11/1993 Cote et al 437/195

5,651,857 7/1997 Cronin et al 156/644.1

5,667,632 9/1997 Burton et al 438/570

5,719,089 2/1998 Cherng et al 438/637

FOREIGN PATENT DOCUMENTS

63-253647 10/1988 lapan .
2251722 7/1992 United Kingdom .

OTHER PUBLICATIONS

Joshi, "A New Damascene Structure for Submicrometer Interconnect Wiring," IEEE Electron Device Letters, vol. 14, No. 3, Mar. 1993, pp. 129-132.

Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," Jun. 11-12, 1991, VMIC Conference, IEEE, pp. 144-152.

Kenney et al., "A Buried-Plate Trench Cell for a 64—Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 14—15.

Primary Examiner—-Janet C. Baxter

Assistant Examiner—Rosemary Ashton

Attorney, Agent, or Firm—McDermott, Will & Emery

[57] ABSTRACT

Sub-micron contacts/vias and conductive lines in a dielectric layer are formed by etching through a photoresist mask containing openings having a dimension less than that achievable by conventional photolithographic techniques. Such minimal size openings are obtained by initially forming an oversized opening by conventional photolithographic techniques and then reducing the size of the opening by forming a sidewall spacer, such as a dielectric sidewall spacer, within the opening. In an embodiment, a plurality of openings are formed in first photoresist layer, each of which openings is provided with a sidewall spacer. The openings are filled with a filling material, such as a second photoresist material, and the photoresist mask and sidewall spacers are removed leaving a plurality of masking portions containing the second photoresist material. An underlying conductive layer is then etched through masking portions to form conductive lines having sub-micron dimensions.

30 Claims, 6 Drawing Sheets