Apparatus, circuit and method of controlling memory initialization

US008069312B2

(12) UIllt€d States Patent (10) Patent No.: US 8,069,312 B2 Nasu (45) Date of Patent: Nov. 29, 2011 (54) APPARATUS, CIRCUIT AND METHOD OF (56) References Cited CONTROLLING MEMORY INITIALIZATION U.S. PATENT DOCUMENTS (75) Inventor: Yasuyuki Nasu: Tokyo (JP) 7,809,962 B2 * 10/2010 Chang et a1‘ ,,,,,,,,,,,,,, H 713/300 (73) Assignee: NEC Corporation, Tokyo (JP) FOREIGN PATENT DOCUMENTS ( * ) Notice: Subject to any disclaimer, the term of this ‘LP _ E-324453 12/1993 patent is extended or adjusted under 35 cued by examlner U.S.C. 154(b) by 576 days. Primary Examiner * Hiep Nguyen (21) APP1' N05 12/292,139 (74) Attorney, Agent, or Firm * McGinn IP Law Group, (22) Filed: Nov. 12, 2008 PLLC (65) Prior Publication Data (57) ABSTRACT Us 2009/0187717 A1 1111- 23, 2009 An apparatus includes a first memory Which includes a plu_ _ _ _ _ rality of memory regions, a second memory Which stores (30) Forelgn Apphcatlon Pnonty Data initializing information indicating Whether each of the memory regions is initialized, the second memory controlling Jan. 17, 2008 (JP) ............................... .. 2008-007616 a Coherency between the first memory and a Cache memory’ (51) Int Cl and a control circuit Which initializes a memory region based G0;$F 2/00 (200601) on the initializing information When accessing the memory (52) U.S. C1. ........................................ .. 711/141 reglm (58) Field of Classification Search ...................... .. None See application file for complete search history. 15 Claims, 5 Drawing Sheets 100 MEMORY CONTROLLER 4 I MEMORY ACCESS REQUESTOR /I r ------------------------ --r ------------------------- "L\, 1 I 12 1 1 I I A t I I I I I I I 1 1 I I I DIRECTORY MEMORY MAIN MEMORY I I CONTROLLER CONTROLLER I I I 1 1 1 1 I I I I 1 1 1 1 1 1 I _ _ _ _ _ _ _ _ _ _ _ _ . _ _ _ - _ _ _ _ _ _ _ _ _ _ _ _ - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___| DIRECTORY MAIN MEMORY MEMORY -V 3 N 2

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