mi iiiiiii ill mi mi lyyii ii|jiiijpi mil mil mi mi mi
(12) United States Patent
Chae et al.
(io) Patent No.: (45) Date of Patent:
US 7,072,238 B2 Jul. 4, 2006
(54) SEMICONDUCTOR DEVICE CAPABLE OF GENERATING RIPPLE-FREE VOLTAGE INTERNALLY
(75) Inventors: Dong-Hyuk Chae, Seoul (KR);
Young-Ho Lim, Gyeonggi-do (KR)
(73) Assignee: Samsung Electronics Co., Ltd.,
Suwon-si (KR)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 11/025,001
(22) Filed: Dec. 28, 2004
(65) Prior Publication Data
US 2006/0044884 Al Mar. 2, 2006
(30) Foreign Application Priority Data
Sep. 2, 2004 (KR) 10-2004-0069927
(51) Int. CI.
G11C 7/00 (2006.01)
(52) U.S. CI 365/226; 365/189.09; 365/189.07;
365/185.21
(58) Field of Classification Search 365/226,
365/189.09, 189.07, 185.21 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,519,656 A 5/1996 Maccarrone et al.
5,642,309 A 6/1997 Kim et al.
5,689,460 A * 11/1997 Ooishi 365/189.07
5,881,014 A * 3/1999 Ooishi 365/226
6,031,778 A * 2/2000 Makino et al 365/226
6,038,178 A * 3/2000 Oh 365/189.09
6,061,270 A 5/2000 Choi
6,335,881 Bl 1/2002 Kim et al.
6,370,062 Bl 4/2002 Choi
FOREIGN PATENT DOCUMENTS
JP 2002-150786 5/2002
KR 2003-0057885 7/2003
OTHER PUBLICATIONS
English language abstract of Korean Publication No. 20030057885.
English language abstract of Japanese Publication No. 2002150786.
* cited by examiner
Primary Examiner—Tuan T. Nguyen
(74) Attorney, Agent, or Firm—Marger Johnson &
McCollom, PC.
![[blocks in formation]](http://www.google.fr/patents?id=qZ96AAAAEBAJ&hl=fr&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=fr&q=&cds=1&sig=ACfU3U0cAQ9lFPyhycIDtU4_yr3Bv5050g&edge=0&edge=stretch&ci=487,587,258,18)
![[blocks in formation]](http://www.google.fr/patents?id=qZ96AAAAEBAJ&hl=fr&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=fr&q=&cds=1&sig=ACfU3U0cAQ9lFPyhycIDtU4_yr3Bv5050g&edge=0&edge=stretch&ci=128,768,381,32)
A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit for supplying current to a second power line from the first power line, a PMOS transistor coupled between a first power line and the second power line, and a controller for controlling the drive current of the PMOS transistor in response to the voltage on the second power line.
17 Claims, 6 Drawing Sheets