(12) United States Patent ao) Patent No.: us 6,750,157 Bi
Fastow et al. (45) Date of Patent: Jun. 15,2004
5,617,357 A 4/1997 Haddad et al.
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FOREIGN PATENT DOCUMENTS
WO 9907000 2/1999
T.Y. Chan, et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, vol. EDL-8, No. 3, March 1987, pp. 93-95. Hisa, Yukun, et al., "MNOS Traps and Tailored Trap Distribution Gate Dielectric MNOS," 1980, Japanese Journal of Applied Physics, vol.19, Supp. 19-1, pp. 245-248. Fukuda, et al., Novel N20-Oxinitridation Technology for Forming Highly Reliable EEPROM Tunnel Oxide Films, IEEE Elec. IEEE Elec. Device Lett., 12 (Nov. 1991) 587. White, et al., A Low Voltage Sonos Nonvolatile Semiconductor Memory Technology, IEEE Trans. Components, Packaging & Manufacturing Tech., 20 (Jun. 1997) 190.
Primary Examiner—Richard Elms
Assistant Examiner—Doug Menz
(74) Attorney, Agent, or Firm—Amin & Turocy, LLP
One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.
12 Claims, 10 Drawing Sheets