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US006567287B2
(12) United States Patent (io) Patent No.: US 6,567,287 B2
Scheuerlein (45) Date of Patent: May 20,2003
(54) MEMORY DEVICE WITH ROW AND
COLUMN DECODER CIRCUITS ARRANGED
IN A CHECKERBOARD PATTERN UNDER A
PLURALITY OF MEMORY ARRAYS
(75) Inventor: Roy E. Scheuerlein, Cupertino, CA
(US)
(73) Assignee: Matrix Semiconductor, Inc., Santa Clara, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/896,814
(22) Filed: Jun. 29, 2001
(65) Prior Publication Data
US 2002/0136045 Al Sep. 26, 2002
Related U.S. Application Data
(60) Provisional application No. 60/277,794, filed on Mar. 21, 2001, provisional application No. 60/277,815, filed on Mar. 21, 2001, and provisional application No. 60/277,738, filed on Mar. 21, 2001.
(51) Int. CI. G11C 5/02
(52) U.S. CI 365/51; 365/63; 365/230.03;
365/230.06
(58) Field of Search 365/51, 63, 230.03,
365/230.06, 230.01
(56) References Cited
U.S. PATENT DOCUMENTS
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OTHER PUBLICATIONS
Naji et al., "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM," ISSCC 2001 Visual Supplement, pp. 94-95, 404-405 (2001).
Mohsen et al., "The Design and Performance of CMOS 256K Bit DRAM Devices," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 610-618 (Oct. 1984). Kawamoto et al, "A 288K CMOS Pseudostatic RAM," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 619-623 (Oct. 1984).
Naji et al., "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM," Digest of Technical Papers of the 2001 IEEE International Solid-State Circuits Conference, ISSCC 2001/Session 7/Technology Directions: Advanced Technologies/7.6, 2 pages (Feb. 6, 2001).
Primary Examiner—Hoai Ho
(74) Attorney, Agent, or Firm—Brinks Hofer Gilson & Lione
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The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
26 Claims, 8 Drawing Sheets
