(12) United States Patent ao) Patent No.: us 6,207,222 Bi
Chen et al. (45) Date of Patent: Mar. 27,2001
PCT Search Report Dated Nov. 5, 1998.
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Primary Examiner—Shrive Beck
Assistant Examiner—Paul D. Strain
(74) Attorney, Agent, or Firm—Thomason Moser &
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The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
6 Claims, 7 Drawing Sheets