An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the...http://www.google.fr/patents/US5511219?utm_source=gb-gplus-shareBrevet US5511219 - Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core
Mechanism for implementing vector address pointer registers in system having ...