OPTIMIZED BUFFERING FOR JTAG
BOUNDARY SCAN NETS
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for improving implementing JTAG boundary scan control nets generally and, more particularly, to a method and/or architecture for (i) reducing the area which is needed for the net routing and (ii) controlling placement of wires on the die after final layout is completed.
BACKGROUND OF THE INVENTION
Referring to FIG. 1, a conventional JTAG boundary scan control signal routing of an application specific integrated circuit (ASIC) 10 is shown. The JTAG signal routing of the ASIC 10 is buffered in a tree structure. The starting point for the tree is typically located somewhere in the center region of the die. In some instances the JTAG boundary scan gates can be placed elsewhere manually. From the starting point the trees fan out to all different sides of the ASIC 10. Therefore, the ASIC 10 will have JTAG boundary scan signal buffers all over the die. Also, routes will go through the center of the die. Because there are several control nets which can go to each I/O cell (not shown, surrounding the ASIC 10), uncontrolled routing occurs and increases congestion problems.
Conventional approaches manually place JTAG boundary scan gates before routing in an attempt to reduce unnecessary routing. However, current netlists which go into layout do not contain sufficient buffering of the high fanout JTAG boundary scan control nets. Therefore, insertion of buffers is done by layout tools based on distances, maximum ramp times or similar requirements, but never driven by the order of I/Os. The result of the buffering is a tree structure across the die. Furthermore, each design has to be handled individually, since no common solution exists.
Conventional boundary scan methodologies are used to test I/Os (i.e., input/output circuitry to connect a chip to the external world) on silicon. There is a set of required boundary scan cells for every set of I/Os to be tested. The boundary scan cells can be placed by a placement tool (or manually in front of the respective I/Os to avoid any timing issues). Flip flops (not shown) in the scan chain are then connected together as a register chain. The placement tool can place the boundary scan cells far away from the respective I/Os, particularly when memories (or other dedicated blocks) are placed in front of the I/Os.
Referring to FIG. 2, a circuit 20 is shown illustrating a conventional boundary scan connection with the boundary scan cells 22«-22« outside the I/O cells 24«-24«. Trying to connect the boundary scan cells 22«-22«, which are scattered over the entire die, can cause timing problems. Since the boundary scan flip flops are connected in a chain, routing issues cause severe hold time violations, thereby causing the chain to fail. However, placing the boundary scan cells 22«-22« manually is very time consuming (there typically exist hundreds of cells in a single device). For example, the manual placement process can take a number of days in a standard size design. Additionally, there is a clock tree at the top level to clock the boundary scan flip flops. Therefore, managing a reasonable skew at chip level is challenging, time consuming and area consuming. Furthermore, since more I/O cells are continually being added inside the I/O devices, timing modeling of the I/O devices need to be constantly updated.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising one or more groups of boundary scan cells, one or more
5 group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group
10 buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.
The objects, features and advantages of the present invention include providing a method and/or architecture for
15 implementing optimized buffering for JTAG boundary scan nets that may (i) buffer scan nets in a way which reflects the order of the I/Os around the die, (ii) allow buffering cell placement and net routing tools to achieve optimal results automatically, (iii) provide universal JTAG boundary scan
20 designs, (vi) implement boundary scan cells inside the I/O cells, (v) implement boundary scan flip flops without a clock tree, (vi) meet hold times for the boundary scan chain, (vii) reduce crosstalk and noise impact of the scan connection, (viii) improve flip flop performance, (ix) provide power
25 savings, (x) reduce turnaround time, and/or (xi) have no additional area cost.
BRIEF DESCRIPTION OF THE DRAWINGS
30 These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
FIG. 1 is a block diagram of a conventional JTAG 35 boundary scan net;
FIG. 2 is a block diagram of a typical boundary scan connection with boundary cells outside the I/O cells;
FIG. 3 is a block diagram of a preferred embodiment of the present invention; 40 FIG. 4 is a flow chart illustrating an operation of the present invention;
FIG. 5 is a block diagram of a boundary scan connection in conjunction with the present invention;
FIG. 6 is a block diagram of a typical scan connection; 45 FIG. 7 is a block diagram of a scan connection in accordance with the present invention;
FIG. 8 is a block diagram of a typical scan flip flop; and
FIG. 9 is a block diagram of a scan flip flop in accordance with the present invention;
DETAILED DESCRIPTION OF THE
Referring to FIG. 3, a block diagram of a system (or 55 circuit) 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 may be configured to improve the overall routing of JTAG boundary scan control nets in an ASIC design. The circuit 100 may be configured to reduce the area which is needed for the net 60 routing and to provide control of where wires will be located on the die after final layout is completed. The system 100 may be configured to optimize buffering for JTAG boundary scan nets. An example of a JTAG boundary scan net may be found in the IEEE Standard Test Access Port and Boundary65 Scan Architecture, published Feb. 15, 1990 and revised on Jun. 17, 1993, which is hereby incorporated by reference in its entirety.