A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region,...http://www.google.fr/patents/US20040041236?utm_source=gb-gplus-shareBrevet US20040041236 - Merged mos-bipolar capacitor memory cell
Numéro de demande: 10/230,929 Numéro de publication: US 2004/0041236 A1 Date de dépôt: 29 août 2002 Brevet délivré: US6838723 ( Date de délivrance 4 janv. 2005)
