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[blocks in formation]

in system memory j Where:

xdb_addr_reg is Transmit Address Register
xdb_ctrl_reg is Transmit Control Register

Fig. 5

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1

METHOD AND SYSTEM FOR
DYNAMICALLY APPENDING A DATA
BLOCK TO A VARIABLE LENGTH
TRANSMIT LIST WHILE TRANSMITTING
ANOTHER DATA BLOCK OVER A SERIAL 5
BUS

CROSS-REFERENCE TO RELATED
APPLICATION

10

The present application is related to U.S. patent application Ser. No. 08/313,680, still pending, entitled "Method And System For Matching Packet Size For Efficient Transmission Over a Serial Bus," U.S. patent application Ser. No. 08/312,854, still pending entitled "Acyclic Cable Bus Hav- 15 ing Redundant Path Access", U.S. patent application Ser. No. 08/313,679, still pending entitled "Method For Generating Topology Map For A Serial Bus", U.S. patent application Ser. No. 08/313,483, now U.S. Pat. No. 5,504,757 entitled "Method For Selecting Transmission Speeds For 20 Transmitting Data Packets Over A Serial Bus", U.S. patent application Ser. No. 08/312,746, still pending entitled "Method And System For Determining Maximum Cable Segments On A Serial Bus Having Multiple Transmission Rates", and U.S. patent application Ser. No. 08/313,490, still 25 pending entitled "Method And System For Automatically Generating A Read Response Packet With Speed Matching Over A Serial Bus", and all filed of even date herewith by the inventors hereof and assigned to the assignee herein, and incorporated by reference herein. 30

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates, generally, to data transmission over a high performance serial bus, and more partial- 35 larly, to being able to append data blocks to data structures to transmit data across a serial bus network. More specifically, the invention relates to an apparatus and method capable of appending data to control data structures or data blocks prior to transmission over a serial bus network. 40

2. Description of the Related Art

The IEEE has proposed a new high performance serial bus standard under the P1394 standard. P1394 is a serial input/output bus whose physical media is a cable that 45 consists of three shielded twisted pairs. PI394 allows a tree topology interconnect of nodes, systems or devices, for reducing the time typically required for turnaround among the nodes. P1394 can operate at multiple transmission rates, such as approximately 100 megabits per second, 200 mega- 50 bits per second, and 400 megabits per second, and has universal interconnect capabilities for desktop systems, peripheral devices such as printers, hard disks, digital camera.

Under P1394, data transmission packets require control 55 data structures or data blocks for identifying source and destination, length, and command information. Once the data structure is received by a destination node, the information within the data structure is used to generate a new data structure or data block for return transmission to the 60 original source of the data structure. Once the data structure has been reformatted, a request in memory is made to locate the data sought by the initial read request within the original data structure. Unfortunately, waiting until after the data structure has been reformatted increases the amount of 65 turnaround time needed to retrieve the data requested by the original source node.

2

Accordingly, what is needed is a way to dynamically link data to the data structure being reformatted so that, upon completion of the reformatting of the original data structure, the data requested is already linked for transmission, thus reducing turnaround time at the destination node before retransmission to the original source node. Also, what is needed is a way of linking the next data block for processing and transmission in order to increase the amount of data processed and transmitted.

SUMMARY OF THE INVENTION

It is therefore one object of the present invention to provide data transmission over a high performance serial bus.

It is another object of the present invention to be able to append data blocks to data structures for transmitting data across a serial bus.

It is yet another object of the present invention to provide an apparatus and method capable of appending data to control data structures or data blocks prior to transmission over a serial bus.

The foregoing objects are achieved as is now described. According to the present invention, a computer system allows for a hardware structure to participate in the transmission of PI394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features. This also has the advantage of eliminating excessive system bus I/O commands to other hardware elements for the transmission of the P1394packets.

The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1A depicts a data processing system in the form of a personal computer in which the present invention can be employed is depicted;

FIG. IB is a block diagram of a personal computer system illustrating the various components of personal computer system in accordance with the present invention;

FIG. 2 is a block diagram of a data packet according to the present invention;

FIG. 3 is a block diagram of a transmit packet register according to the present invention;

FIG. 4 is a block diagram of a transmit address register according to the present invention;

FIG. 5 is a block diagram of a data flow dynamic packet linking according to the present invention;

FIG. 6 is a flowchart depicting the operation of the data flow according to the FIG. 5; illustrating the dynamic appending of a data block to a variable length transmit list

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