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PREPARATION OF COMPOSITE HIGH-K
DIELECTRICS
FIELD OF THE INVENTION 5
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of high-K dielectric layers in semiconductor devices.
BACKGROUND OF THE INVENTION 1°
Fabrication of semiconductor devices, such as a metaloxide-semiconductor (MOS) integrated circuit, involves numerous processing steps. In a semiconductor device, a gate dielectric, typically formed from silicon dioxide 15 ("oxide"), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and 20 drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many present processes employ features, such as gate conductors and interconnects, which have less than 0.18 jum critical dimension. As feature sizes continue to 25 decrease, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, rela- 30 tively small die area.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device 35 dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given 40 way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate 45 oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
As a result of the continuing decrease in feature size, gate oxide thickness has been reduced so much that oxides are approaching thicknesses on the order of ten angstroms (A). 50 Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 50 A thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such a thin gate oxide by a quantum mechanical tunneling effect. In this 55 manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. As a result, a 60 net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage WT may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such 65 defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pin
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holes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice.
A more promising approach to further increasing gate dielectric capacitance may be to increase the permittivity of the gate dielectric. Permittivity, E, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, E0. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
K=e/e0
While silicon dioxide (sometimes simply referred to as "oxide") has a dielectric constant of approximately 3.9, other materials have higher K values. Silicon nitride ("nitride"), for example, has a K of about 6 to 9 (depending on formation conditions). Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta205), barium strontium titanate ("BST"), and lead zirconate titanate ("PZT"). Using a high-K dielectric material for a gate dielectric would allow a high capacitance to be achieved even with a relatively thick dielectric layer. For example, a nitride gate dielectric with a K of 7.8 and a thickness of 100 angstroms is substantially electrically equivalent to an oxide gate dielectric (K about 3.9) having a thickness of about 50 angstroms. For even higher-K dielectric materials, even thicker gate dielectric layers could be formed while maintaining capacitance values higher than are possible with even very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased.
One problem which has been reported relating to integration of high-K dielectric materials is oxidation of silicon by certain high-K dielectric materials when the high-K dielectric material is formed directly on a silicon substrate. Since oxidation results in formation of what may be referred to as a "standard-K" dielectric material, some of the benefit of the high-K dielectric material is considered to be lost. In addition, reactions considered adverse between the high-K dielectric material and standard-K dielectric materials may also occur.
Thus, a method of forming a relatively high-K dielectric material which either overcomes or takes advantage of such reactions, and which provides the electrical advantages of a higher K is needed.
SUMMARY OF THE INVENTION
The present invention, in a first embodiment, relates to a method of making a semiconductor device having a composite layer, including the steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a high-K dielectric material and a dielectric precursor material to form a composite layer having at least two sub-layers of at least one of the high-K dielectric material and the dielectric precursor material.
The present invention, in a second embodiment, relates to a method of making a semiconductor device having a composite dielectric layer formed by exposing the composite layer to annealing conditions including an elevated temperature to form a composite dielectric layer.
The present invention further relates to a semiconductor device having a composite layer, including a semiconductor substrate; and alternating sub-layers of a high-K dielectric material and a second material, the sub-layers forming a composite layer on the semiconductor substrate, the composite layer having at least two sub-layers of at least one of
the high-K dielectric material and the second material, wherein the second material is one of a dielectric precursor material and a second high-K dielectric material. The semiconductor device having a composite layer, when subjected to annealing conditions as described above, may be transformed into a semiconductor device having a composite dielectric layer.
Thus, the present invention relates to a high-K dielectric material which overcomes and takes advantage of previously disfavored reactions between dielectric materials, and relates to a method of making a composite dielectric layer which may include a reaction product of the high-K dielectric material and the dielectric precursor material or a new dielectric material, which is obtained by subjecting the composite layer to annealing conditions.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional view of a field effect transistor including an embodiment of a composite dielectric layer in accordance with the present invention.
FIG. 2 is a schematic cross-sectional view of a semiconductor substrate with a first sub-layer applied thereto in accordance with the present invention.
FIG. 3 is a schematic cross-sectional view of a semiconductor substrate with first and second sub-layers applied thereto in accordance with the present invention.
FIG. 4 is a schematic cross-sectional view of a semiconductor substrate with first, second and third sub-layers applied thereto in accordance with the present invention.
FIG. 5 is a schematic cross-sectional view of a semiconductor substrate with first through fifth sub-layers applied thereto in accordance with the present invention.
FIG. 6 is a schematic cross-sectional view of a semiconductor substrate with first through fourth sub-layers applied thereto in accordance with the present invention.
FIG. 7 is a schematic cross-sectional view of one embodiment of a semiconductor substrate following a step of annealing.
FIG. 8 is a schematic cross-sectional view of another embodiment of a semiconductor substrate following a step of annealing, similar to that shown in FIG. 7.
FIG. 9 is a schematic cross-sectional view of yet another embodiment of a semiconductor substrate following a step of annealing, similar to that shown in FIGS. 7 and 8.
FIG. 10 is a schematic flow diagram showing the basic steps in a process of making a semiconductor device in accordance with the present invention.
DETAILED DESCRIPTION
As used herein, the term "dielectric precursor material" refers to a material which is capable of forming a dielectric material upon exposure to an elevated temperature and any other appropriate conditions, such as a selected atmosphere.
Such dielectric precursor materials include, for example, silicon, aluminum, hafnium, zirconium, yttrium, titanium, tantalum, lanthanum, cesium, tungsten, magnesium, zinc, barium, strontium, bismuth, niobium, scandium and combinations of these and other materials. A person of skill in the art may recognize other suitable dielectric precursor materials. The dielectric precursor materials may form either standard-k or high-K dielectric materials upon exposure to elevated temperatures.
As used herein, the term "standard-K dielectric material" refers to a dielectric material having a K up to about 10.
Such standard-K dielectric materials include, for example, silicon dioxide, which has a K of about 4, silicon oxynitride, which has a K of about 4-8 depending on the relative content of oxygen and nitrogen, and silicon nitride, which has a K of about 6-9.
As used herein, the term "mid-K dielectric material" refers to a dielectric material having a K in the range from about 10 to about 20. Such mid-K dielectric materials include, for example, composite materials such as hafnium silicate, which has a K of about 14, and hafnium silicon oxynitride, which has a K of about 16, depending on the relative content of oxygen and nitrogen, and hafnium silicon nitride, which has a K of about 18.
As used herein, the term "high-K dielectric material" refers to a dielectric material having a K of about 20 or more. Such high-K dielectric materials include, for example, Hf02, Zr02, Ta205, others identified more fully below, and composites of these, as described more fully below.
Approximate K-values or, in some cases, a range of K-values, are shown below in Table 1 for several exemplary dielectric materials. It is understood that the present invention is not limited to the specific dielectric materials disclosed herein, but may include any appropriate high-K dielectric materials and standard-K dielectric materials (derived from the dielectric precursor material described hereinbelow) which are known and are compatible with the remaining elements of the semiconductor device with which the dielectric materials are to be used.
TABLE 1
It is noted that the K-values, or relative permittivity, for both standard-K and high-K dielectric materials may vary to some degree depending on the exact nature of the dielectric material and on the process used to deposit the material. Thus, for example, differences in purity, crystallinity and stoichiometry, may give rise to variations in the exact K-value determined for any particular dielectric material.
As used herein, when a material is referred to by a specific chemical name or formula, the material may include nonstoichiometric variations of the stoichiometrically exact formula identified by the chemical name. For example, tantalum oxide, when stoichiometrically exact, has the chemical formula Ta205. As used herein, the term "tantalum oxide" may include variants of stoichiometric Ta205, which may be referred to as Ta^O^,, in which either of x or y vary by a small amount. For example, in one embodiment, x may
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vary from about 1.5 to 2.5, and y may vary from about 4.5 to about 5.5. In another embodiment, x may vary from about 1.75 to 2.25, and y may vary from about 4 to about 6. Such variations from the exact stoichiometric formula fall within the definition of tantalum oxide. Similar variations from 5 exact stoichiometry are included when the chemical formula for a compound is used. For example, again using tantalum oxide as an example, when the formula Ta205 is used, Ta^O^, as defined above, is included within the meaning. Thus, in the present disclosure, exact stoichiometry is intended only 10 when such is explicitly so stated. As will be understood by those of skill in the art, such variations may occur naturally, or may be sought and controlled by selection and control of the conditions under which materials are formed.
Here and in all numerical values in the specification and 15 claims, the limits of the ranges and ratios may be combined.
As used herein, the term "anneal" or "annealing" refers to a step or process in which a material is exposed to an elevated temperature for a time. The annealing may be a discrete step of annealing, such as a RTA, or it may be part 20 of another step, such as a CVD, which is carried out at an elevated temperature. In either case, annealing includes exposure to an elevated temperature, and may include appropriate additional conditions, such as a selected atmosphere and pressure, for a selected period of time. 25 Semiconductor Devices
The present invention is described hereinbelow in terms of a common semiconductor device, specifically, a metal oxide semiconductor field effect transistor (MOSFET) formed on a silicon substrate. An embodiment of the present 30 invention in a MOSFET is shown in FIG. 1. The present invention is not limited to this illustrative embodiment, however, and may be applied to any semiconductor device in which a dielectric layer is needed, for example, as a gate dielectric in a FET, as a gate dielectric in a floating gate 35 EEPROM flash memory device, in a SONOS-type flash memory device, such as the Mirror-BitTM SONOS-type flash memory device available from AMD. Thus, it is to be understood that the present invention is not limited to the specific illustrative embodiments described below. 40
The present invention relates to semiconductor devices and to methods of making the semiconductor devices. In a first embodiment, the semiconductor device includes a composite layer including a plurality of alternating sub-layers of a high-K dielectric material and a dielectric precursor mate- 45 rial which have been deposited on the semiconductor substrate. The composite layer has at least two sub-layers of at least one of the high-K dielectric material and the dielectric precursor material. Examples of the first embodiment are shown in FIGS. 4-6. 50
In a second embodiment, the semiconductor device includes a composite dielectric layer including a plurality of alternating sub-layers of a high-K dielectric material and a dielectric material formed from the dielectric precursor material upon annealing at a high temperature. As a result of 55 annealing the device including the composite layer of the first embodiment, the device including the composite dielectric layer of the second embodiment is formed. In one embodiment, the composite dielectric layer includes alternating sub-layers of a high-K dielectric material and a new 60 dielectric material. In one embodiment, the new dielectric material is a standard-K dielectric material, and in another embodiment the new dielectric material is a second high-K dielectric material which is distinct from the first (originally deposited) high-K dielectric material. In another 65 embodiment, the composite dielectric layer includes a reaction product, made up of elements of the high-K dielectric
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material and of the dielectric precursor material or of the newly formed dielectric material. In one embodiment, the composite dielectric layer comprises a reaction product of the high-K material and the newly formed dielectric material which is a metal silicate.
In one embodiment, at the annealing temperature, the dielectric precursor material first is oxidized to form a new, second dielectric material. The new dielectric material, in one embodiment, is a standard-K dielectric material. The new dielectric material, in another embodiment, is a high-K dielectric material. As a result, alternating sub-layers of high-K dielectric material and the new dielectric material are formed. In one embodiment, at the annealing temperature, at least a portion of the alternating sub-layers combine or react with each other, at least at the interfaces of the alternating sub-layers, to form the composite dielectric layer which includes a reaction product of the dielectric materials of the respective sub-layers. Examples of the second embodiment are shown in FIGS. 7-9.
As described above, in the present invention, two embodiments of a semiconductor device are produced, with the device of the first embodiment capable of being transformed into the device of the second embodiment by a high temperature annealing step.
The reaction product and/or the composite dielectric layer as a whole may have a K-value intermediate the K-values of the high-K dielectric material and the new dielectric material which is formed from the dielectric precursor material. In an embodiment in which a reaction product is formed, the reaction product is a composite of the high-K dielectric material and the new dielectric material, so may have a K value which is intermediate the K values of the respective dielectric materials from which the reaction product was formed. Thus, in some embodiments, the reaction product and/or the composite dielectric layer as a whole may be a mid-K dielectric material. In some embodiments, the reaction product and/or the composite dielectric layer as a whole may have a high K value, i.e., may be a high-K dielectric material.
In one embodiment, the semiconductor substrate is a bulk silicon substrate. In one embodiment, the semiconductor substrate is a silicon-on-insulator semiconductor substrate. In another embodiment, the semiconductor substrate is a p-doped silicon substrate. Suitable semiconductor substrates include, for example, bulk silicon semiconductor substrates, silicon-on-insulator (SOI) semiconductor substrates, siliconon-sapphire (SOS) semiconductor substrates, and semiconductor substrates formed of other materials known in the art. The present invention is not limited to any particular type of semiconductor substrate.
FIG. 1 is a schematic cross-sectional view of a MOSFET 100. The MOSFET 100 includes, for example, a p-doped silicon substrate 102, an n-doped source region 104, an n-doped drain region 106, a gate 108, a gate composite dielectric layer 114, and a channel region 112.
Not shown in FIG. 1 are additional parts of a working semiconductor device, such as electrical conductors, protective coatings and other parts of the structure which would be included in a complete, working semiconductor device. These additional parts are not necessary to the present invention, and for simplicity and brevity are neither shown nor described, but could be easily added as will be understood by those of skill in the art.
The gate composite dielectric layer 114 illustrated in FIG. 1 has a structure including five sub-layers; thus the gate dielectric 114 is a composite dielectric layer. The gate composite dielectric layer 114 illustrated in FIG. 1 has two
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sub-layers 114a and 114c of a first material and one sublayer 114fc of a second material, and two sub-layers U4rp of a reaction product obtained by the reaction or combination of the first and second materials of the sub-layers 114fl-114c. One of the first and second materials is the 5 high-K dielectric material and the other is the dielectric precursor material.
The composite dielectric layer 114 illustrated in FIG. 1 comprises three alternating sub-layers 114a-114c, separated by reaction product sub-layers U4rp. The composite dielec- 10 trie layer 114 could comprise any number of additional alternating sub-layers 114a-114a>, where w represents a letter corresponding to the number of sub-layers, from 3 to about 10, with each pair of sub-layers separated by a reaction product sub-layer U4rp, following the annealing 15 step. In one embodiment, the composite layer includes four alternating sub-layers (ff>=4), in another, five alternating sub-layers (ff>=5), and in another, six alternating sub-layers (w=6), and in yet another, seven alternating sub-layers (w=7). Higher numbers of alternating sub-layers may be 20 present, but from 3 to about 7 alternating sub-layers a>=3-7) are considered most useful at present. In each case, the sub-layers of dielectric materials, following the annealing step, are separated by a reaction product sub-layer U4rp. As described more fully below, the relative thickness of these 25 sub-layers may be selected and controlled as desired.
The foregoing paragraph applies equally to the composite layer 110 of the first embodiment, shown in FIGS. 4-6, except that there are no sub-layers of a reaction product in the first embodiment. Thus, the composite layer I 10 could 30 comprise any number of additional alternating sub-layers HOa-HOw, where w represents a letter corresponding to the number of sub-layers, from 3 to about 10.
The composite layer 110 shown in FIG. 4 includes two similar sub-layers 110a and 110c, and a dissimilar third 35 sub-layer, llOfc. In one embodiment, the two similar sublayers llOfl and 110c each comprise a high-K dielectric material, and the dissimilar third sub-layer HOfc comprises a dielectric precursor material. In another embodiment, the opposite arrangement is used, i.e., the two similar sub-layers 40 llOfl and 110c each comprise a dielectric precursor material, and the dissimilar third sub-layer HOfc comprises a high-K dielectric material. In another embodiment, the dielectric precursor material is replaced by a new dielectric material. In one embodiment, the new dielectric material is a second 45 high-K dielectric material. In one embodiment, the second high-K dielectric material is different from the first, originally deposited high-K dielectric material.
In the embodiment shown in FIG. 5, the composite layer 110 comprises five sub-layers, HOa-llOe, alternating in a 50 pattern which continues the alternating pattern described above for three sub-layers llOa-llOc.
In the embodiment shown in FIG. 6, the composite layer 110 comprises four sub-layers, HOa-llOrf, alternating in a pattern which is similar to that described above for three 55 sub-layers HOa-llOc, except that the lowermost and uppermost sub-layers, 110a and llOrf, are different in this embodiment. In other embodiments, the number of sub-layers may vary as described above, but the sub-layers alternate in each such embodiment. 60
As noted above with respect to FIG. 6, in an embodiment in which there is an even number of sub-layers in the composite layer 110, the lowermost sub-layer may be a high-K dielectric material and the uppermost sub-layer may be a dielectric precursor material. In another embodiment 65 having an even number of sub-layers in the composite layer 110, the lowermost sub-layer may be a dielectric precursor
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material and the uppermost sub-layer may be a high-K dielectric material. FIG. 6 is applicable to either even number sub-layer case.
Thus, the number of sub-layers HOa-HOw of the composite layer 110 may be odd or even, and the uppermost and lowermost sub-layers may be either the high-K dielectric material, the dielectric precursor material, or the new dielectric material and the number of sub-layers of each type may be equal or unequal.
The first sub-layer may be the high-K dielectric material or the dielectric precursor material, and conversely, the second sub-layer may be the high-K dielectric material or the dielectric precursor material.
In one embodiment, the dielectric precursor material includes silicon. In one embodiment, the silicon is deposited as polycrystalline silicon (also known simply as "poly"). In another embodiment, the silicon is deposited as amorphous silicon. In one embodiment, the dielectric precursor material comprises elements other than or in addition to silicon, such as germanium or gallium, which will form a dielectric material upon annealing.
In another embodiment, the dielectric precursor material comprises at least one of aluminum, hafnium, zirconium, yttrium, titanium, tantalum, lanthanum, cesium, tungsten, magnesium, zinc, barium, strontium, bismuth, niobium and scandium and combinations thereof, or combinations thereof with silicon.
The dielectric precursor material is a material which, when oxidized under the annealing conditions, forms the new dielectric material, as described above.
In one embodiment, the high-K dielectric material includes at least one of hafnium oxide (Hf02), zirconium oxide (Zr02), tantalum oxide (Ta205), barium titanate (BaTi03), titanium dioxide (Ti02), cesium oxide (Ce02), lanthanum oxide (La203), tungsten oxide (W03), yttrium oxide (Y203), bismuth silicon oxide (Bi4Si2012), barium strontium oxide (Ba1_;cSr:);03), barium strontium titanate (BST) (Ba^SrJiO,), PZN (PbZn^Nb^O,), and PST (PbSc^Taj^C^). In addition to the foregoing high-K dielectrics, other high-K dielectric materials, for example, ferroelectric high-K dielectric materials such as lead zirconium titanate, lead lanthanum titanate, strontium bismuth tantalate, bismuth titanate, strontium titanate, lead zirconium titanate (PZT (PbZr.Ti^C^)) and barium zirconium titanate may be suitably used in the present invention. Other high-K dielectric materials known in the art also may be used in the present invention.
The reaction product U4rp includes the elements of both the high-K dielectric material and the new dielectric material formed from the dielectric precursor material. For example, in an embodiment in which the high-K dielectric material is hafnium oxide and the dielectric precursor material is silicon, the reaction product is a silicate compound containing hafnium, silicon and oxygen, Hf/Si/O. In one embodiment, the reaction product is hafnium silicate, HfSi04. Thus, in an embodiment in which the high-K dielectric material contains a metal atom, e.g., in the form of a metal oxide, and the dielectric precursor material is silicon, the reaction product is a metal-containing silicate.
In another embodiment, the high-K dielectric material is zirconium oxide and the dielectric precursor material is silicon, and the composite dielectric layer includes zirconium, silicon and oxygen. In one such embodiment, the reaction product is zirconium silicate, ZrSi04. In yet another embodiment, the high-K dielectric material is cesium oxide and the dielectric precursor material is silicon, and the composite dielectric layer includes cesium, silicon and oxy
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