Current controlled delay circuit

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CURRENT CONTROLLED DELAY CIRCUIT

TECHNICAL FIELD

Embodiments of the invention generally relate to the field of delay circuitry, and more specifically, to a current controlled delay circuit.

BACKGROUND

A conventional delay cell 100 is shown in FIG. 1. The delay cell 100 includes a plurality of Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs), such as 104 and 106. MOSFETs 104 and 106 comprise a differential pair, which switches the current 110 from one output leg to another output leg based on the voltage difference between input voltages 112 and 114. When the difference between input voltages 112 and 114 is greater than zero, current 110 flows in output leg 120. If the difference between the input voltages is less than zero, current flows in output leg 122.

The delay cell 100 includes a current source 108, voltagecontrolled resistances 124 and 126, and output load capacitances 130 and 132. The voltage-controlled resistances 124 and 126 control the delay of the circuit 100. The delay is defined by the time it takes the RC (voltage controlled resistance-load capacitance product) voltage rise of one output leg of the delay cell to equal the RC voltage decay of the other output leg after the difference of inputs 114 and 118 transitions, switching the current 110 from one output leg to the other output leg. This is modeled by the following equation: IR(l-e_1/RC)=I RE_1/*C, where I is the current 110 provided by the current source 108 and t is the time delay. Solving for t, the delay through delay cell 100 is t=RCln(2). At low output voltage, the voltage controlled resistances 124 and 126 are modeled by the following equation: R=l/Gm= l/B(Vc-Vzffiv), where Gm is an NMOS transconductance, Vc is the control voltage 102, WTHN is the NMOS threshold voltage, and B is the product of the W/L ratio (width divided by length of the transistor), the oxide capacitance Cox, and the MOSFET channel mobility. In a ring oscillator composed of N delay cells, the frequency of the circuit is approximately

1 = B(VC - Vthn) 2N x t 2/VCln(2)'

Further discussion of conventional delay cells can be found in the articles "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John Maneatis, IEEE Journal of Solid-State Circuits: Vol. 31, No. 11, November 1996, pp. 1723-1732; and "A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability" by Patrik Larsson, IEEE Journal of Solid-State Circuits: Vol. 34, No. 12, December 1999, pp. 1951-1960.

Since the output voltage of the delay cell 100 is between

0 and IR, and R can vary by as much as 5 times to modulate the delay, the value of I must track R to maintain sufficient output voltage swing (VOut-majt^r) m me circuit to sustain the signal through a series of delay cells, such as in a delay line or ring oscillator. A feedback structure must -be used to set the product IR equal to a constant reference voltage (yout-aiax^vref)- This makes the delay of the conventional delay cell 100 sensitive to changes in I. Since l^KEp/R is set by a compensated feedback loop, changes to

1 occur much more slowly than changes in R for varying control voltage Vc. Rapid changes in Vc and R can cause

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short-term amplitude modulation in "V'0ut-max> which will cause delay modulation. "V'Out-max can also drop low enough within the delay cell to prevent the triggering of the next delay cell in the series, disabling the voltage controlled

5 oscillator (VCO) or delay line of which it is a part of. A solution to this problem is to limit the voltage control signal (Vc) modulation bandwidth of the VCO or delay line utilizing this cell. For a phase lock loop (PLL) or delay locked loop (DLL), limiting the modulation bandwidth of

10 the loop's VCO or delay line directly limits the bandwidth of the system.

The conventional delay cell also has a limited linear voltage control range. Beyond a certain range of Vc, the voltage-controlled resistances 124 and 126 are no longer a 15 linear function of Vc. PLL stability design is more difficult using VCOs with non-linear frequency control and can generate PLLs with greater output noise.

BRIEF DESCRIPTION OF DRAWINGS

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The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

25 FIG. 1 is a circuit diagram illustrating a conventional delay cell.

FIG. 2 is a circuit diagram illustrating one embodiment of a current controlled delay circuit using an RC based delay. FIG. 3 is a circuit diagram illustrating an alternative 30 embodiment of a current controlled delay circuit using a linear ramp based delay.

FIG. 4a is a functional representation of the startup condition of the delay circuit shown in FIG. 2. 35 FIG. 4b is a functional representation of the delay circuit shown in FIG. 2 after the differential pair has switched one of the currents between the output legs.

FIG. 4c is a functional representation of the delay circuit shown in FIG. 2 after the cross-coupled pair has switched 40 one of the currents between the output legs.

FIG. 5 is a functional representation of the delay circuit shown in FIG. 3 after the differential pair has switched one of the currents between the output legs.

FIG. 6 is a flow diagram illustrating one embodiment of 45 a method of using current to control delay.

DETAILED DESCRIPTION

Embodiments of a current controlled delay circuit are

50 described. In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in

55 order not to obscure the understanding of this description. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the

go invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in

65 any suitable manner in one or more embodiments.

Referring to FIG. 2, a circuit diagram illustrating one embodiment of a current controlled delay circuit 200 is 3

shown. In one embodiment, the delay circuit 200 may be used in a current controlled ring oscillator. In one embodiment, the delay circuit 200 may be used in a current controlled delay line. The delay circuit 200 includes 20 one or more current generators, such as 206 or 208, to generate 5 two currents, lt (202) and I2 (204), of constant sum. In one embodiment, one or more of the current generators are Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs). In one embodiment, one or more of the current generators are current sources. 10

The delay circuit 200 includes a plurality of MOSFETs, such as 226, 228, 230, or 232. The MOSFETs 226 and 228 make up a differential pair, which switches current lt from one output leg to another output leg based on the voltage difference between input voltages 236 and 238. The differ- :5 ential pair is modeled as a switch such that when the difference between input voltages 236 and 238 is greater than zero, current lt flows in output leg 214. If the difference between input voltages 236 and 238 is less than zero, current lt flows in output leg 216. 20

MOSFETs 230 and 232 comprise a cross-coupled pair, which switches the current I2 from one output leg to another output leg based on the voltage difference between output voltages 210 and 212. The cross-coupled pair is modeled as a switch such that when the difference between the output 25 voltages 210 and 212 is greater than zero, current I2 204 flows in output leg 216. If the difference is less than zero, current I2 flows in output leg 214.

The delay circuit 200 includes a load coupled to the 3Q cross-coupled pair and the differential pair. The load may be a fixed load or a variable load. In one embodiment, the load includes two resistances 218 and 220. In one embodiment, the load includes one or more resistors. In one embodiment, the load includes one or more MOSFETs. In one 3J embodiment, the load includes a voltage-controlled resistance, such as the voltage-controlled resistance 124 or 126 shown in FIG. 1. In one embodiment, the delay circuit 200 includes output capacitance loads 222 and 224 on the output legs. In one embodiment, capacitances 222 and 224 4Q are the input capacitances of another delay cell.

FIG. 4a is a functional representation of the startup condition of the delay circuit 200 shown in FIG. 2, with a fixed resistive load. FIG. 4b is a functional representation of the delay circuit 200 after the differential pair switches 45 current lx from a second output leg 216 to a first output leg 214. FIG. 4c is a functional representation of the delay circuit 200 after the cross-coupled pair switches current I2 from the second leg 216 to the first leg 214.

In the example delay circuit 200, the first leg 214 of the 50 circuit 200 has a resistance 218 of value R and a capacitance 222 of value C. A second leg 216 of the circuit 200 has a resistance 220 of value R and a capacitance 224 of value C. The RC values of both legs of the circuit 200 are held constant, and the delay of the circuit 200 is altered by 55 changing \1 and I2. At the initial condition, shown in FIG. 4a, the first leg 214 of the delay circuit 200 has no current flowing in, while the second leg 216 of the delay circuit 200 gets both currents, lt and I2. Therefore, the first leg 214 is charged to approximately 0V, while the second leg 216 is go charged to (I1+I2)*R. So for the initial condition, the voltage W1 (210) of the first leg 214 is V^OV, and the voltage V2 (212) of the second leg 216 is V2=(I1+I2)*R.

When the difference between input voltages 236 and 238 transitions, shown in FIG. 4b, lt is switched to the first leg 65 214 by the differential pair made up of MOSFETs 226 and 228. This causes the first leg to begin charging to lt*R. The

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second leg 216 only has I2 current, so it begins to discharge to I2*R. When the output voltages of the two legs become equal (V1=V2), the next delay stage switches. At the time the next stage switches, shown in FIG. 4c, the cross-coupled pair 206 switches I2 to the first leg 214, which causes the first leg 214 to further charge to (I1+I2)*R. The second leg 216 has no current, so the second leg 216 discharges to approximately 0V. This sets up the initial condition of the delay circuit for the next time the differential input voltage difference transitions. This setup condition has V1=(I1+I2)*R and V2=0V.

The delay is defined by the time it takes the RC voltage rise of one output leg of the delay cell to equal the RC voltage decay of the other output leg after the difference of inputs voltages 236 and 238 transitions, switching the current lt from one output leg to the other output leg. The delay of circuit 200 is described by the following output voltage equivalence equation:

...

Therefore, the time delay t=-RCln(l+I1+I2/2I1). The sum Ic of the two currents is held constant: IC=I1+I2. For an N stage ring oscillator, the frequency can be modeled according to the following equation:

2/1

f = —■

J INRCtlc

The delay circuit 200 may also have a variable load, such as the voltage controlled resistance 102 shown in FIG. 1. This allows delay circuit 200 to have two controls. The variable resistance may be used to configure the center frequency or delay of a current controlled oscillator (ICO) or a current controlled delay (ICD) in order to reach a larger frequency or delay range. For example, while a voltage controlled oscillator (VCO) could use the current control to reach an approximately 2x range around a center frequency ^center under regular operation, the variable resistance control could be utilized to vary FCENTER by 8-10x in order to extend the total frequency range of the VCO. This could be done using fixed settings or dynamic digital or analog control. If done dynamically, the current control may act as a fine frequency control while the variable resistance acts as the coarse control.

The two controls could also be used to create a resistorless Phase Locked Loop (PLL) or Delay Locked Loop (DLL). In this case, the current control would be operated by the output of the phase detector and would operate at a number of discrete settings, such as high/low or high/low/ center. This mimics the control zero produced by the resistor in the loop of a typical charge pump type PLL, causing a substantially instantaneous frequency shift for the duration of the phase detector correction. The variable resistance would control the average frequency and take as input a damped voltage generated by a charge pump or op-amp with a capacitive loop filter.

Referring to FIG. 3, a circuit diagram illustrating one embodiment of a current controlled delay circuit 300 is shown. The delay circuit 300 includes two current sources 340 and 342 to generate two currents, lx (302) and I2 (304) of constant sum. The delay circuit 300 includes a differential pair made up of MOSFETs 306 and 308 to switch lt from one leg of the circuit to another leg of the circuit. The delay circuit 300 includes a cross-coupled pair made up of MOSFETs 318 and 328 to switch I2 from one leg of the circuit to another leg of the circuit.