A system and associated methodology are disclosed for characterizing soft error or failure rates of electronic circuit elements, where the elements are suitable for use as non-memory peripheral logic in semiconductor memory devices, and where the probability of such soft error or failure rates increases...http://www.google.fr/patents/US20040187050?utm_source=gb-gplus-shareBrevet US20040187050 - Test structure and method for accurate determination of soft error of logic components
Test structure and method for accurate determination of soft error of logic ...
