METHOD OF MANUFACTURING
BACKGROUND OF THE INVENTION 5
This invention relates to a method of manufacturing a semiconductor device. More particularly, it relates to improvements in a method of bonding a metallic interconnection to a semiconductor region through an open- 1Q ing in an oxide film deposited on the semiconductor region.
As an integrated circuit becomes higher in density and larger in scale, the production of acceptable circuits becomes lower. In this regard, the problem of discon- 15 nection especially during the formation of a metallic interconnection is a serious factor. The metallic interconnection is usually made of aluminum (Al), and is formed in such a way that after depositing aluminum by vacuum evaporation or sputtering, it is etched into a 20 required pattern by photolithography. At this time, it often occurs that the aluminum is not deposited in a film of uniform thickness at a stepped part of the pattern. In addition, the deposited aluminum is sometimes lost at the stepped part during the course of forming the pat- 2$ tern. Since, in general, these difficulties are more serious the larger the level difference of the stepped part, there has been proposed that the level difference of a stepped part be reduced and that a stepped part having a gentle slope be formed. 30
Now, a prior-art method will be described using a P-channel Al-gate MOS FET as an example. FIGS. 1(a) to 1(c) are vertical sectional views which show a part of a semiconductor wafer during the essential steps of a prior-art method of forming openings for contact and 35 metallic interconnections.
As shown in FIG. 1(a), a silicon oxide film (Si02 film) 2 is formed on a selected area of a silicon single-crystal substrate 1 of the N-conductivity type. Thereafter, the subtrate is heated in an atmosphere containing diborane 40 (B2H6), to diffuse boron thereinto and to form source and drain regions of the P-conductivity type 3. Subsequently, as shown in FIG. (b), a thick Si02 film 4 is formed on the semiconductor substrate 1 after removing the Si02 film 2. Further, openings 5 for bonding 45 metallic interconnections to the source and drain regions 3 and an opening 6 for forming a gate insulating film and for connecting an Al interconnection with the gate insulating film are provided in the Si02 film 4 by the photolithographic etching. Subsequently, as shown 50 in FIG. 1(c), the gate insulating film 7 is formed on that part of the semiconductor substrate 1 which is exposed through the opening 6. Thereafter, Al is deposited onto those parts of the source and drain regions 3 which are exposed through the openings 5, onto the gate insulat- 55 ing film 7 and onto the SK>2 film 4, and it is patterned into a required shape so as to form the metallic interconnections 8. Thus, the semiconductor wafer of the Pchannel Al-gate MOS FET is completed.
FIGS. 2(a) and 2(b) are enlarged sectional views each 60 showing the state of the Al interconnection 8 at the source or drain region 3.
Ordinarily, those end parts of the SK>2 film 4 which face the opening for the source or drain region 3 have a steep slope as shown in these figures. As illustrated in 65 FIG. 2(a), the thickness ti of the Al interconnection 8 overlying the end part of the S1O2 film 4 is less than the thickness t2 of the Al interconnection 8 overlying a flat
part of the Si02 film 4. In some cases, the Al interconnection 8 becomes broken as illustrated in FIG. 2(b).
FIG. 3 is a plan view in which the portion shown in FIG. 2(a) is seen from the side of the metallic interconnection. Lines A and B in FIG. 3 correspond to points A and B in FIG. 2(a), respectively. Numeral 9 designates a photoresist film. In the step of the selective removal of the deposited Al for forming the pattern of the Al interconnections 8, a constriction often develops in the Al interconnection 8 as shown in FIG. 3.
The breaking and constriction of the Al interconnections 8 are attributed to the fact that the end parts of the Si02 film 4 facing the opening have an abrupt inclination. To moderate the effect of such a steep stepped part, there has heretofore been proposed a method in which an Si02 film is highly doped with phosphorus to reduce the inclination. With this method, however, it is difficult to obtain a small opening. Another disadvantage is that, since a high-temperature treatment at above 1,050° C. is required, the diffusion of the impurity proceeds rapidly.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an improved method of manufacturing a semiconductor device.
Another object of this invention is to provide an improved method of manufacturing a semiconductor device which can prevent electrode interconnections from being constricted or broken.
Still another object of this invention is to provide an improved method of manufacturing a semiconductor device which permits the formation of fine openings by self-alignment and which sharply enhances the density of integration.
Yet another object of this invention is to provide an improved method of manufacturing a semiconductor device which reduces the capacitance between a gate electrode and a source or drain electrode, thus making high speed operation possible.
Further objects of this invention will become apparent from the following detailed description taken with reference to the drawings illustrative of the preferred embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(a) to 1(c) are vertical sectional views of a semi-conductor wafer during the principal steps of a prior-art method,
FIGS. 2(a) and 2(b) are enlarged sectional views each showing the state of an Al interconnection,
FIG. 3 is a plan view showing the state of the Al interconnection,
FIGS. 4(a) to 4(d) are vertical sectional views of a semi-conductor wafer during the principal steps of a method embodying this invention,
FIG. 5 is a graph showing the relationship between the bird beak angle Ob and the thickness of an underlying Si02 film,
FIGS. 6(a) and 6(b) are vertical sectional views of a semi-conductor wafer during intermediate steps of a method of another embodiment of this invention,
FIGS. 7(a) to 7(/) are vertical sectional views of a semi-conductor wafer during the principal steps of applying this invention to the manufacture of an Al-gate SOS (silicon-on-sapphire) complementary MOS FET,