115 communicate via port 113. In an alternate embodiment (not shown), the storage device 115 is an external storage device, which is connected to the host computer via a data bus. Those skilled in the art will appreciate that various communication buses known in the art can be used to 5 transfer data between the drive and the host system.
As shown in FIG. 1A, the system includes controller 101, which is coupled to fibre channel ports 102 and 103, buffer memory 114 and microprocessor 100. Interface 116 serves to couple microprocessor bus 107 to microprocessor 100. A 10 read only memory ("ROM") omitted from the drawing is used to store firmware code executed by microprocessor 100.
Controller 101 can be an integrated circuit (IC) that comprises of various functional modules, which provide for 15 the writing and reading of data stored on storage device 115 or to other devices through fibre channel ports 102 and 103.
Microprocessor 100 is coupled to controller 101 via interface 116 to facilitate transfer of data, address, timing and control information. Buffer memory 114 is coupled to 20 controller 101 via ports to facilitate transfer of data, timing and address information.
Data flow controller 117 is connected to microprocessor bus 107 and to buffer controller 118. Disk formatter 110 formats data that is flowing through system 100A, either 25 from storage device 115 or from fibre channel ports 102/103.
Fibre channel controllers ("A") 104 and ("B") 108 include programmable registers and state machine sequencers that interface with ports 102 and 103. The fibre channel controllers 104 and 108 provide fibre channel control for ports 102 30 and 103.
Microcontrollers ("A") 105 and ("B") 106 allow customization of fibre channel sequences and control Fibre channel controllers 104 and 108 through a microcontroller interface module (not shown). ECC engine 111 provides error cor- 35 recti on for system 100 A.
Various memory modules exists in controller 101, for example, memory 105A, 106A and 118A.
TAP controller 119, described in more detail below, is used to control the BIST operation for various memory 40 modules. Information from TAP controller 119 maybe sent via TAP interface ("TAP I/F") 120 and accessed outside system 100A. As discussed above, in some systems TAP I/F 120 may not be available and hence it becomes difficult to perform the BIST tests. 45
The adaptive aspects of the present invention, allow storage controller 101 to perform the BIST in dual modes. In a first mode, as shown in FIG. IB, if the TAP I/F 120 is present and detected by controller 101, the BIST may be performed so that BIST results are accessible via TAP I/F 50 120. In another mode, as shown in FIG. 2, internal register bits are used to initiate the BIST operation and the results are accessible to processor 100 via register reads. The modes may be programmed by firmware using an internal configuration register 116A. 55
FIG. IB shows tap controller 119 coupled to a memory controller 105B that controls the BIST operation for memory 105A. Instructions 116G from TAP controller 119 are sent to memory BIST controller 105B and after the test is performed, the results 116H are sent to TAP controller 60 119. The results 116H may be accessed by a system external to storage controller 101 via TAP I/F 120.
FIG. 2 shows a block diagram where the BIST operation is initiated by using internal register commands. Internal register 116B includes control bits that are used to trigger a 65 BIST operation. Processor 100 may set the control bits. Control bits 116F (also shown as 116D) are sent to BIST
controller 105B via a multiplexer ("Mux") 116C. Mux 116C also receives instructions 116G from TAP controller 119. Instructions 116G may be selected to initiate a BIST operation (as shown in FIG. IB) based on firmware programming.
Memory BIST controller 105B starts and controls the BIST operation for memory 105A. The results 116H are sent to register 116A with status bits 116E. The status bits 116E may be used to generate an interrupt for processor 100. This notifies processor 100 that BIST results are available. Results 116H may also be made available via TAP interface 120.
It is noteworthy that although FIG. 2 shows two registers 116A and 116B, only a single register may be used to initiate the BIST operation described above with respect to FIG. 2 and below with respect to FIG. 3.
FIG. 3 shows a process flow diagram for conducting a BIST operation, according to one aspect of the present invention. Turning in detail to FIG. 3, in step S300, the BIST process is started. In step S302, the process determines whether to use the TAP controller 119 (as shown in FIG. IB) or an internal register value, as shown in FIG. 2, to initiate the BIST operation.
If the TAP controller 119 is used, then in step S310, standard TAP controller 119 instructions (116G) are used to initiate the BIST operation. The test results may be accessed in step S312 using TAP interface 120.
If register control bits are used (step S302), then in step S304, control bits are set in internal register 116B. In step S306, control bits 116F are used to activate memory BIST controller 105B (shown as 116D via Mux 116C). In step S308, after the test is completed status bits 116E are set in register 116A so that processor 100 may be notified of test completion and provide access to the test results.
In one aspect of the present invention, a user can use the internal register technique to initiate a BIST operation and hence no TAP Interface 120 is required. In another aspect of the present invention, a user has the flexibility of initiating a BIST operation either by using TAP controller instructions or internal register control bits.
Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.
What is claimed is:
1. A method for initiating a built in self test ("BIST") operation for memory modules, comprising of:
determining whether a test access port ("TAP") controller instruction or an internal register control bit of an internal register is to be used for initiating the BIST operation;
sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and
setting a status bit in the internal register after the BIST operation is complete.
2. The method of claim 1, further comprising: sending the TAP instruction to the memory BIST controller; and
providing access to a BIST operation result via a TAP interface.
3. The method of claim 1, wherein the internal register is also used to set a bit that selects between the TAP instruction and the internal register control bit for initiating the BIST operation.
4. The method of claim 1, wherein a processor is used to read the status bit from the internal register and access a BIST operation test result.