CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects...http://www.google.fr/patents/US20050127971?utm_source=gb-gplus-shareBrevet US20050127971 - Redundant single event upset supression system
Numéro de demande: 10/735,489 Numéro de publication: US 2005/0127971 A1 Date de dépôt: 12 déc. 2003 Brevet délivré: US7023235 ( Date de délivrance 4 avr. 2006)
