A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific...http://www.google.fr/patents/US5217916?utm_source=gb-gplus-shareBrevet US5217916 - Method of making an adaptive configurable gate array
Method of making an adaptive configurable gate array
