METHOD OF PROGRAMMING FLASH
REFERENCE TO PRIORITY APPLICATIONS
 This application is a divisional of U.S. application Ser. No. 11/833,564, filed Aug. 3, 2007, which is a divisional of U.S. application Ser. No. 11/205,245, filed Aug. 16, 2005 (now U.S. Pat. No. 7,269,068), which claims priority to KoreanApplicationNo. 2004-86669, filed Oct. 28,2004. The disclosures of U.S. application Ser. No. 11/833,564 and U.S. Pat. No. 7,269,068 are hereby incorporated herein by reference.
FIELD OF THE INVENTION
 The present invention relates to integrated circuit memory devices and methods of programming same and, more particularly, to nonvolatile memory devices and methods of programming nonvolatile memory devices.
BACKGROUND OF THE INVENTION
 Nonvolatile memory devices keep data stored therein even if a power source is disconnected thereto. Among nonvolatile memories, a flash memory has a function of electrically and collectively erasing data of cells. Therefore, flash memories are widely used for computers and memory cards. The flash memory is divided into a NOR flash memory and a NAND flash memory in accordance with the connection state between cells and bit lines. In general, since the NOR flash memory has large current consumption, the NOR flash memory is disadvantageous to high integration but can support high speed operation. Since the NAND flash memory uses smaller cell current than the NOR flash memory, the NAND flash memory is advantageous to high integration.  The NAND flash memory includes a memory cell array as a storage region for storing information. The memory cell array consists of a plurality of blocks and each block consists of a plurality of cell strings (also referred to as NAND strings). A page buffer circuit is provided in the flash memory in order to store data in the memory cell array or to read data from the memory cell array. As well known, the memory cells of the NAND flash memory are erased or programmed using Fowler-Nordheim tunneling current. Methods of erasing and programming a NAND flash electrically erasable and programmable read only memory (EEPROM) are disclosed in U.S. Pat. No. 5,473,563 entitled "Nonvolatile Semiconductor Memory" and in U.S. Pat. No. 5,696,717 entitled "Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability".  FIG. 1 illustrates changes in a wordline voltage according to a common programming method. Referring to FIG. 1, in order to correctly control the value of threshold voltages of flash memory cells, the flash memory cells are programmed by an incremental step pulse programming (ISPP) method. A circuit for generating a program voltage in accordance with the ISPP method is disclosed in U. S. Pat. No. 5,642,309, entitled "Auto-Program Circuit in a Nonvolatile Semiconductor Memory Device". A program voltage Vpgm in accordance with the ISPP programming method sequentially increases as program loops of a program cycle are repeated, as illustrated in FIG. 1. Each program loop consists of a program period and a program verification period as is well known. The program voltage Vpgm increases by a predetermined increment AVpgm and program time is maintained uniform with respect to the program loops.  However, when a sharply increased program voltage Vpgm is generated in the respective program steps, cou
pling noise increases. This sharply increased program voltage Vpgm is characterized by very large AV/At variations. The coupling noise also typically increases as the integration density of a memory device increases and the distance between adjacent signal lines is reduced (i.e., as the capacitance coupling increases between adjacent signal lines, such as adjacent wordlines, adjacent string selection lines (SSL), or adjacent ground selection transistors (GST)). In order to solve these problems, the flash memory device may generate a sequentially increased program voltage Vpgm_ramp using a high voltage ramping circuit instead of generating the sharply increased program voltage Vpgm.
 FIG. 2 illustrates change in a wordline voltage when a program inhibit method using a self-boosting scheme is applied. Referring to FIG. 2, according to the program inhibit method using the self-boosting scheme, blocks to be programmed are first selected and then, a pass voltage Vpass is applied to all the wordlines of the selected blocks. All the memory cells included in the blocks are precharged to a predetermined level by the pass voltage Vpass applied to the wordlines. Then, the sequentially increased program voltage Vpgm_ramp is applied to the wordline of the cell to be programmed among the memory cells. At this time, the applied program voltage Vpgm_ramp is sequentially generated in accordance with the ISPP scheme illustrated in FIG. 1. The program voltage (Target Vpgm) that is targeted during each step of ISPP sequentially increases in the form of steps by the high voltage ramping circuit.
 FIG. 2 illustrates a case in which the level of the targeted program voltage (Target Vpgm) is 14 V and a case in which the level of the targeted program voltage (Target Vpgm) is 20V, respectively. Each of the targeted program voltages is generated by five ramping steps. The level of the ramped program voltage Vpgm_ramp is preferably higher than the pass voltage Vpass applied to the wordlines. However, as illustrated in FIG. 2, as the level of the targeted program voltage (Target Vpgm) is reduced, the level of the ramped program voltage Vpgm_ramp becomes lower than the level of the pass voltage Vpass (refer to the portionmarked with a dotted circle of FIG. 2). Such a problem occurs since the step of the high voltage ramping circuit performing ramping is fixed even when the level of the targeted program voltage Target Vpgm is low. When the level of the ramped program voltage is lower than the level of the pass voltage Vpass, the boosting efficiency deteriorates and the reliability of programming deteriorates.
SUMMARY OF THE INVENTION
 Embodiments of the present invention include methods of programming a non-volatile memory array by applying a pass voltage to a plurality of unselected word lines in the non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. This sequentially ramped voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage. According to further aspects of these embodiments, the step of applying a pass voltage to a plurality of unselected word lines includes reducing an elevated pass voltage by an amount equal to a threshold voltage of a MOS transistor. Moreover, the step of applying a sequentially ramped program voltage to a selected word line includes generating a sequentially ramped program voltage using an incremental step pulse programming (ISPP) method.  Still further embodiments of the present invention include a flash memory device. This flash memory device includes a memory array having a plurality of NAND strings